What is a Launch edge?
In synchronous design, certain activity or certain amount of computation is done
within a clock cycle.
Memory elements like flip-flop and latches are used in
synchronous designs to hold the input values stable during the clock cycle while the
computations are being performed.
Beginning of the clock cycle initiate the activity and by the end of the clock cycle
activity has to be completed, and results have to be ready.
Memory elements in a design transfer data from input to output on either rising or the falling edge of the
clock. This edge is called the active edge of the clock.
During the clock cycle, data propagates from output of one memory element, through
the combinational logic to the input of second memory element.
The data has to meet a certain arrival time requirement at the input of the second memory element.
As shown in the above figure, the active edge of the clock(shown in red) at the first
memory element makes new data available at the output of the memory element and
starts data to propagate through the logic.
Input ‘in’ has risen to one before the first active(rising) edge of the clock, but this value of ‘in’ is transferred to Q1 pin only when clock rises.
This active edge of the clock is called the launch edge, because it
launches the data at the output of first memory element, which eventually has to be
captured by next memory element along the data propagation path.
What is Capture edge?
As we discussed in previous question, the way synchronous circuits work, certain
amount of computation has to be done within a clock cycle.
At the launch edge of the clock, memory elements transfer fresh set of data at the output pin of the launching memory elements. This new data, ripples through the combinational logic that carries
out the stipulated computation.
By the end of the clock cycle, new computed data has to be available at the next set of
memory elements. Because next active clock edge, which signifies the end of one
clock cycle, captures the computed results at the D2 pin of the memory element and
transfers the results to the Q2 pin for the subsequent clock cycle.
This next active edge of the clock, show in blue at figure 1, is called the capture edge, as it really is
capturing the results at the end of the clock cycle.
There are some caveats to be aware of. The data D2 has to arrive certain time before
the capture edge of clock, in order to be captured properly. This is called setup time
requirement, which we will discuss later.
Although it is said that computation has to be done within one clock cycle, it is not
always the case. In general, it is true that computation has to be done within one clock
cycle, but many times, computation can take more than one cycle. When this happens
we call it a multi cycle path.