What is setup time?
For any sequential element e.g. latch or flip-flop, input data needs to be stable when
clock-capture edge is active.
Actually, data needs to be stable for a certain time before clock-capture edge activates, because if data is changing near the clock-capture edge, sequential element (latch or flip-flop) can get into a metastable state, and it could take unpredictable amount of time to resolve the metastability and could settle at at state which is different from the input value, thus can capture unintended value at the
output.
The time requirement for input data to be stable before the clock capture edge
activates is called the setup time of that sequential element
Timing Propagation from one Flipflop to another Flipflop
Following is a simple structure where output of a flop goes through some stages of
combinational logic, represented by pink bubble and is eventually samples by
receiving flop.
Receiving flop, which samples the FF2_in data, poses timing requirements on the input data signal.
The logic between FF1_out to FF2_in should be such that signal transitions could
propagate through this logic fast enough to be captured by the receiving flop.
For a flop to correctly capture input data, the input data to flop has to arrive and become
stable for some period of time before the capture clock edge at the flop.
This requirement is called the setup time of the flop.
Usually, you’ll run into setup time issues when there is too much logic in between two flop or the combinational delay is too small. Hence this is sometimes called max delay or slow delay timing issue, and the constraints is called max delay constraint.
In figure there is max delay constraint on FF2_in input at receiving flop. Now you can
realize that max delay or slow delay constraint is frequency dependent.
If you are failing setup to a flop and if you slow down the clock frequency, your clock cycle time
increases, hence, you’ve larger time for your slow signal transitions to propagate
through and you’ll now meet setup requirements.
Typically, your digital circuit is run at certain frequency which sets your max delay constraints. Amount of time the signal falls short to meet the setup time is called setup
or max, slack or margin
Setup time failure of a Flipflop
Following figure describes visually a setup failure. As you can see that first flop
releases the data at the active edge of clock, which happens to be the rising edge of the
clock. FF1_out falls sometime after the clk1 rises.
The delay from the clock rising to the data changing at output pin is commonly
referred to as clock to out delay. There is finite delay from FF1_out to FF2_in through
some combinational logic for the signal to travel.
After this delay signal arrives at second flop and FF2_in falls. Because of large delay
from FF1_out to FF2_in, FF2_in falls after the setup requirement of second flop,
indicated by the orange/red vertical dotted line.
This means input signal to second flop FF2_in, is not held stable for setup time requirement of the flop and hence this flop goes metastable and doesn’t correctly capture this data at it’s output.
As you can see one would’ve expected ‘Out’ node to go low, but it doesn’t because of
setup time or max delay failure at the input of the second flop.
Setup time requirement dictates that input signal be steady during the setup window ( which is a certain time before the clock capture edge ).
As mentioned earlier if we reduce frequency, our cycle time increases and eventually
FF2_in will be able to make it in time and there will not be a setup failure. Also notice
that a clock skew is observed at the second flop.
The clock to second flop clk2 is not aligned with clk1 anymore and it arrives earlier, which exacerbates the setup failure.
This is a real world situation where clock to all receivers will not arrival at same time
and designer will have to account for the clock skew. We’ll talk separately about clock
skew in details
