How does lockup latch help with avoiding hold violations?
If you understand hold time check very well, or if you have been analyzing the
waveforms for hold time check, you will realize that hold time issues start happening
as soon as launch and capture clock edge align with each other or are very close to
each other.
We know that more spread apart launch and capture edge are in such a way that launch
edge is later than the capture edge, less of a hold time concern there is.
We know that when launch and capture clock are from the same source and have same
waveform, the greatest distance between an edge in launch clock and an edge in
capture clock can not be greater than clock phase.
Because if try to do that you will approach one of the edge closer on the other side.
If the falling edge of clock is the launch edge and rising edge of clock is capture edge,
we know that launch and capture edge would be a phase apart and as long as launch
edge happens after capture edge, we would have a phase worth of margin for hold
check.
This is true for the case where falling clock edge is capture edge and rising
edge is launching edge. The key is that they are a clock phase apart and launch happens
later than capture.
This is what exactly a lock up latch achieves. It changes the launch edge from rising to
falling edge and capture edge remains rising.
So, we get launch and capture edges to be farthest apart (clock phase) giving us best possible hold time protection.
Also launch happens later than capture, which is what we want. Lets take a look at the figure below
to better understand this.
Here we are assuming launch and capture flops to be rising edge triggered. As shown
in figure before lock up latch, it’s a simple setup and hold check.
The issue is this type of hold check (also called race as launch and capture edges are the same, it is like a
data race), it could be very difficult and expensive to fix this type of hold violations, if launch and captured clock common points are far apart, there could be quite a large
clock uncertainty.
This is very typical for scan or test clocks where last flop in one scan chain is in a specific clock domain and first cell of next scan chain is in a different clock domain. There could be large hold violations for such paths.
Low phase latch, launches data at the falling edge of the clock and remains transparent
during low phase. Essentially by introducing the lockup latch, we moved launch edge
from rising to falling, and now our launch and capture edges are a clock phase apart,
we have a clock phase worth of margin(slack) to meet the hold time requirement.
As shown in figure there can be a large uncertainty between testclock_a and
testclock_b. If you recall from the hold margin equation, larger the clock uncertainty
larger the negative slack that will have to be fixed.
In such situations the lockup latch is introduced between the two chains to address the
hold violation
One has to realize that lockup latch doesn’t come completely free. Because it changes
the launch edge from rising to falling, we are modifying our setup or max timing path
from the original launch flop to capture flop from a full clock cycle to half clock
cycle(clock phase).
Normally you would think of adding lockup latch only if you had
hold issues to begin with which means, there was not a setup problem to begin with.
Because if you had hold problems that means there wasn’t much path delay from the
launch flop to capture flop.
Does location of lockup latch matter? What if in previous example
you moved lockup latch from near launch flop to capture flop?
The location of lockup latch very much matters. When you introduce lockup latch in between two flops, you are essentially breaking timing path into two segments.
One path from the original launch flop to the lockup latch and other timing path from the
lockup latch to the original capture flop.
There is a reason why we didn’t bother about the timing path from the launch flop to
the lockup latch. Original launch flop launches data at rising edge of the clock and low
phase lockup latch captures data at the rising edge of the clock as well.
This could be a hold time issues, but it really is not because we clocked the lockup latch with the same
clock that was clocking the launch flop. In Fact it is essential we do this and place low
phase lockup latch right next to the launch flop.
Doing so will ensure that there is no hold time issue from the launch flop to the lockup latch, as essentially it is the same clock net that is driving both, hence there can not be a data race from the launch flop
to the lockup latch
As shown in this figure, there is a hold check that is supposed to happen from the
launch flop to the lockup latch, but it really is not an issue because of the same clock
edge first launching data and then capturing the data.
Many timing tools understand this configuration and might not report this hold check, and even if timing tool reports this hold check, it should pass.
You can see that once the lockup latch is moved close to capture flop, the hold
violation from the launch flop to the lockup latch becomes the real issue as both clocks
are now different and could come from different domain as we saw in test clock
example and lockup latch are really not serving any purpose to fix the hold violation.
Hence it is vital to place the lockup latch at correct location with correct clock.