What is Double Patterning?
Double patterning is one of several advanced techniques used in the semiconductor industry to continue scaling down device sizes while maintaining performance and manufacturability.
Double patterning is a lithography technique used in VLSI (Very Large Scale Integration) design to overcome limitations in traditional photolithography, particularly as feature sizes shrink in advanced semiconductor manufacturing.
Double patterning lithography is a crucial technique in advanced VLSI manufacturing, particularly as feature sizes continue to shrink beyond the capabilities of traditional lithography methods.
Multiple patterning lithography (MPL) techniques have been used to extend the 193nm lithography to 22nm/14nm nodes.
Possibly further due to the delay of extreme ultra violet lithography and electric beam lithography (EBL) Generally speaking, the MPL consists of double patterning lithography (DPL) and triple patterning lithography (TPL).
There are two main types of DPL with different manufacturing processes:
litho-etch-litho-etch (LELE) and
self-align double patterning (SADP).
Both of them can be extended for triple patterning. The most important issue for multiple patterning technique is how to successfully decompose the layout into several masks that can be manufactured under current 193nm optical lithography.
When the pitch between two patterns is less than the lithography threshold, the patterns have to be separated into different masks. This process is called layout decomposition, or coloring.
There are many studies on MPL layout decompositions at the mask synthesis stage to resolve the coloring conflicts, minimize the stitches, balance the mask density, or even mitigate the undesirable overlay effects.
The double-patterning technology (DPT) that means we can continue to use 193nm lithography to produce features at a 64nm pitch in 20nm processes is a breakthrough for manufacturing but an added complication for design.
In double patterning, features that are too close together to be resolved with conventional lithography are separated onto two masks, which are exposed sequentially, with an etch step in between, to form the necessary densely packed features.
Designers must create layouts that can be split (‘decomposed’) into two layers, a process known as coloring, after map-coloring theory.
Achieving such layouts means following new design rules that encapsulate the limitations of the lithographic process and prohibit two polygons of the same color from having particular geometric relationships.
Physical designers have to work with these new rules during placement and routing, considering the costs of decomposability alongside other costs such as timing, power and area.
The physical verification process also has to change, so that it can show that an entire layout can be successfully split onto two masks in a way that meets the foundry’s specifications.
Achieving decomposability
Although foundries will often decompose a layout themselves so that they can optimize the resultant masks for manufacturability, producing decomposable designs means being able to show that applying the foundry rules to a layout can result in successful mask assignments.
Advantages of Double Patterning
Enhanced Resolution: Enables the creation of smaller features beyond the diffraction limit of traditional photolithography.
Increased Circuit Density: Allows for more transistors to be placed on a chip, improving performance and functionality.
Cost Efficiency: Extends the life of existing photolithography tools without requiring the immediate adoption of more expensive extreme ultraviolet (EUV) lithography.
Challenges and Considerations
Design Complexity: Designers must create layouts that can be effectively split into two patterns without violating design rules or creating unprintable features.
Process Variability: Each lithographic step introduces potential variability and defects, requiring robust testing and calibration.
Increased Cycle Time: The additional steps in the manufacturing process can lead to longer production times and increased costs.
Mask Complexity: The creation of masks for double patterning can be more complex and costly due to the need for precise alignment and additional layers.
Double Patterning Workflow
Layer Preparation
- Show a silicon wafer (rectangle) with a photoresist layer (thin rectangle on top).
First Lithographic Exposure
- Illustrate a mask (showing the first pattern) aligned over the photoresist-coated wafer.
- Arrows can indicate exposure to light, highlighting areas that will be developed.
Development of First Pattern
- Depict the wafer after developing, where the photoresist has been removed from the exposed areas, revealing the first pattern.
Etching Process
- Show the wafer being etched, with the first pattern transferred to the underlying silicon.
- Indicate areas that have been etched away.
Second Lithographic Exposure
- Illustrate the application of a second layer of photoresist over the already processed wafer.
- Show a different mask aligned for the second exposure.
Development of Second Pattern
- Similar to the first pattern, illustrate the development of the second pattern.
Final Etching
- Depict the final etched wafer with both patterns clearly defined, highlighting the completed features.