Variable uvm_sequence_base::starting_phase is deprecated and replaced by two new methods set_starting_phase and get_starting_phase, which prevent starting_phase from being modified in the middle of a phase. This change […]
Most of us, have faced these some issues at least one time in our SystemVerilog programming while using “disable fork”
In UVM, there is a mechanism to be followed when we want to send the transactions from the sequencer to
Why do we use callback mechanism?Callback mechanism is used for altering the behavior of the transactor(also called BFM) without modifying
In SystemVerilog, Downcasting and Virtual Concepts are important concepts used in object-oriented programming (OOP) within the hardware verification environment. These
What is Interface Class? An interface class has nothing to do with the interface construct. It represents the same concept as an interface
Uses of UVM Barrier: uvm_barrier can be used to force a set of independently executing processes (e.g. virtual sequences) to
Wire:- Reg:- Wires and Regs are present from Verilog time-frame. SystemVerilog added a new data type called logic to them.
Makefile The make utility automatically determines which pieces of a large program need to be recompiled, and issues commands to
Dynamic Array: Why do we use Dynamic Array? Example: int my_array []; initial begin my_array = new[4]; //Allocated 4 elements end Example:
