What is Associative Array?
Associative arrays are one of the most versatile and efficient data structures in SystemVerilog. They provide developers with the flexibility […]
System Verilog
Bus functional models (BFM)
Bus Functional Models (BFM) in UVM (Independent Verification Methodology) What is BFM? A Bus Functional Model (BFM) is a
Automatic raise and drop objection with UVM-1.2
Variable uvm_sequence_base::starting_phase is deprecated and replaced by two new methods set_starting_phase and get_starting_phase, which prevent starting_phase from being modified in the middle of a phase. This change
Kill process using “disable fork” and “disable LABEL”
Most of us, have faced these some issues at least one time in our SystemVerilog programming while using “disable fork”
UVM Driver and Sequencer Handshaking
In UVM, there is a mechanism to be followed when we want to send the transactions from the sequencer to
UVM Callback with example
Why do we use callback mechanism?Callback mechanism is used for altering the behavior of the transactor(also called BFM) without modifying
Down Cast and Virtual Concept
In SystemVerilog, Downcasting and Virtual Concepts are important concepts used in object-oriented programming (OOP) within the hardware verification environment. These
Interface Class in System Verilog
What is Interface Class? An interface class has nothing to do with the interface construct. It represents the same concept as an interface
Barrier in UVM
Uses of UVM Barrier: uvm_barrier can be used to force a set of independently executing processes (e.g. virtual sequences) to
Difference between wire, reg and logic
Wire:- Reg:- Wires and Regs are present from Verilog time-frame. SystemVerilog added a new data type called logic to them.