7 Simple points to understand Setup Time in VLSI

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  1. At time T=π‘‡π‘™π‘Žπ‘’π‘›π‘β„Žπ‘’π‘‘π‘”π‘’, Data A is launched from FF1 to FF2. The data needs to make it to FF2 before the next clock edge arrives at FF2 at time π‘‡π‘π‘Žπ‘π‘‘π‘’π‘Ÿπ‘’π‘’π‘‘π‘”π‘’. The next clock edge will arrive after a clock period

πΏπ‘Žπ‘’π‘›π‘β„Ž = π‘‡π‘™π‘Žπ‘’π‘›π‘β„Žπ‘’π‘‘π‘”π‘’

πΆπ‘Žπ‘π‘‘π‘’π‘Ÿπ‘’ = π‘‡π‘π‘Žπ‘π‘‘π‘’π‘Ÿπ‘’π‘’π‘‘π‘”e

2. The clock takes some time to reach FF1 due to the buffers. The launch won’t happen
exactly at T=π‘‡π‘™π‘Žπ‘’π‘›π‘β„Ž_𝑒𝑑𝑔𝑒 but after the delay/latency of the clock buffers.

πΏπ‘Žπ‘’π‘›π‘β„Ž = π‘‡π‘™π‘Žπ‘’π‘›π‘β„Žπ‘’π‘‘π‘”π‘’ + π‘»π’π’‚π’–π’π’„π’‰π’π’‚π’•π’†π’π’„π’š
πΆπ‘Žπ‘π‘‘π‘’π‘Ÿπ‘’ = π‘‡π‘π‘Žπ‘π‘‘π‘’π‘Ÿπ‘’_𝑒𝑑𝑔e

3. As we saw in part 1, once the clock reaches the FF it takes some time to push the data out to the Q pin. We called this time π‘‡π‘π‘ž. This is the 1st delay data A encounters to reach FF2.

πΏπ‘Žπ‘’π‘›π‘β„Ž = π‘‡π‘™π‘Žπ‘’π‘›π‘β„Žπ‘’π‘‘π‘”π‘’ + π‘‡π‘™π‘Žπ‘’π‘›π‘β„Žπ‘™π‘Žπ‘‘π‘’π‘›π‘π‘¦
π·π‘’π‘™π‘Žπ‘¦ =𝑻𝒄𝒒
πΆπ‘Žπ‘π‘‘π‘’π‘Ÿπ‘’ = π‘‡π‘π‘Žπ‘π‘‘π‘’π‘Ÿπ‘’_𝑒𝑑𝑔e

4. Data A will propagate through the combinational path to reach FF2. This is the
2nd delay it encounters.

lπ‘Žπ‘’π‘›π‘β„Ž =π‘‡π‘™π‘Žπ‘’π‘›π‘β„Žπ‘’π‘‘π‘”π‘’+π‘‡π‘™π‘Žπ‘’π‘›π‘β„Žπ‘™π‘Žπ‘‘π‘’π‘›π‘π‘¦
π·π‘’π‘™π‘Žπ‘¦=π‘‡π‘π‘ž+π‘»π’„π’π’Žπ’ƒ
πΆπ‘Žπ‘π‘‘π‘’π‘Ÿπ‘’=π‘‡π‘π‘Žπ‘π‘‘π‘’π‘Ÿπ‘’_𝑒𝑑𝑔e

5. As we saw in part 1, the FF requires the data to arrive some time before the clock edge in order to avoid metastability. We called this time 𝑇𝑠𝑒𝑑𝑒𝑝. Hence, we shouldn’t capture data at π‘‡π‘π‘Žπ‘π‘‘π‘’π‘Ÿπ‘’π‘’π‘‘π‘”π‘’ but at π‘‡π‘π‘Žπ‘π‘‘π‘’π‘Ÿπ‘’π‘’π‘‘π‘”π‘’βˆ’π‘‡π‘ π‘’π‘‘π‘’p

πΏπ‘Žπ‘’π‘›π‘β„Ž =π‘‡π‘™π‘Žπ‘’π‘›π‘β„Žπ‘’π‘‘π‘”π‘’+π‘‡π‘™π‘Žπ‘’π‘›π‘β„Žπ‘™π‘Žπ‘‘π‘’π‘›π‘π‘¦
π·π‘’π‘™π‘Žπ‘¦=π‘‡π‘π‘ž+π‘‡π‘π‘œπ‘šπ‘
πΆπ‘Žπ‘π‘‘π‘’π‘Ÿπ‘’=π‘‡π‘π‘Žπ‘π‘‘π‘’π‘Ÿπ‘’_π‘’π‘‘π‘”π‘’βˆ’π‘»π’”π’†π’•π’–p

6. The clock takes some time to reach FF2 due to the buffers. The capture won’t happen
exactly at π‘‡π‘π‘Žπ‘π‘‘π‘’π‘Ÿπ‘’_π‘’π‘‘π‘”π‘’βˆ’π‘‡π‘ π‘’π‘‘π‘’π‘ but after the delay/latency of the clock buffers.

πΏπ‘Žπ‘’π‘›π‘β„Ž =π‘‡π‘™π‘Žπ‘’π‘›π‘β„Žπ‘’π‘‘π‘”π‘’+π‘‡π‘™π‘Žπ‘’π‘›π‘β„Žπ‘™π‘Žπ‘‘π‘’π‘›π‘π‘¦
π·π‘’π‘™π‘Žπ‘¦=π‘‡π‘π‘ž+π‘‡π‘π‘œπ‘šπ‘
πΆπ‘Žπ‘π‘‘π‘’π‘Ÿπ‘’=π‘‡π‘π‘Žπ‘π‘‘π‘’π‘Ÿπ‘’π‘’π‘‘π‘”π‘’βˆ’π‘‡π‘ π‘’π‘‘π‘’π‘+𝑻𝒄𝒂𝒑𝒕𝒖𝒓𝒆𝒍𝒂𝒕𝒆𝒏𝒄y

7. To make sure a setup violation doesn’t happen, we need to make sure data A arrives
at FF2 before the required capture time.
The difference between the required and arrival time is called the slack. If the slack is positive, we pass setup and if negative, we fail. The launch FF is called the start point of the timing path and the capture FF is called the endpoint.

πΏπ‘Žπ‘’π‘›π‘β„Ž +π·π‘’π‘™π‘Žπ‘¦ ≀ πΆπ‘Žπ‘π‘‘π‘’π‘Ÿπ‘’
π΄π‘Ÿπ‘Ÿπ‘–π‘£π‘Žπ‘™ ≀ π‘…π‘’π‘žπ‘’π‘–π‘Ÿπ‘’π‘‘
π‘‡π‘™π‘Žπ‘’π‘›π‘β„Žπ‘’π‘‘π‘”π‘’ + π‘‡π‘™π‘Žπ‘’π‘›π‘β„Žπ‘™π‘Žπ‘‘π‘’π‘›π‘π‘¦ + π‘‡π‘π‘œπ‘šπ‘ < π‘‡π‘π‘Žπ‘π‘‘π‘’π‘Ÿπ‘’π‘’π‘‘π‘”π‘’ βˆ’ 𝑇𝑠𝑒𝑑𝑒𝑝 + π‘‡π‘π‘Žπ‘π‘‘π‘’π‘Ÿπ‘’π‘™π‘Žπ‘‘π‘’π‘›π‘y

Setup Timing Report

  • The example we have shown is for a full cycle path where the π‘‡π‘π‘Žπ‘π‘‘π‘’π‘Ÿπ‘’π‘’π‘‘π‘”π‘’ comes one clock cycle after π‘‡π‘™π‘Žπ‘’π‘›π‘β„Žπ‘’π‘‘π‘”π‘’.
    β€’ This is not always the case. The capture edge could come half cycle later, multiple cycles later or from another clock.
    o Half cycle paths occur when the launch and capture FFs use different clock edges
    o Multi cycle paths occur when the first capture edge is masked by a control circuit and another edge is used
    Multi clock paths occurs when the launch and capture FFs use different clocks from each other.
    The diagram shows that there could be more than one launch/capture edges combination. The STA tools will consider the worst case (The purple one)1
    β€’ All what we learned still apply and nothing changes. We will just plug different values for the clock edges into the setup equation

π‘»π’π’‚π’–π’π’„π’‰π’†π’…π’ˆπ’† + π‘»π’π’‚π’–π’π’„π’‰π’π’‚π’•π’†π’π’„π’š + π‘»π’„π’π’Žπ’ƒ < π‘»π’„π’‚π’‘π’•π’–π’“π’†π’†π’…π’ˆπ’† βˆ’ 𝑻𝒔𝒆𝒕𝒖𝒑 + 𝑻𝒄𝒂𝒑𝒕𝒖𝒓𝒆𝒍𝒂𝒕𝒆𝒏𝒄y

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