Primetime provides an efficient way to analyze timing at different corners and different operating modes. MMMC (multi-mode multi corner) refers to performing timing analysis at various modes and corner.
What is DMSA in STA?
- Distributed Multi-Scenario Analysis (DMSA) refers to timing analysis at different scenarios in a distributed manner. Scenarios are combination of various operating corners(process, voltage, temperature, RC corners) and different operating modes (functional mode, test mode, sleep mode, read mode, write mode etc).
- Scenarios can be different for timing and power analysis. Some significant scenarios for timing and power are mentioned below,
- RC_worst_slowProcess_HighTemp_LowVoltage: This scenario is generally used for checking setup time. RC_worst indicates the worst values of Resistance and worst values for coupling and ground capacitance on interconnects are taken into the account.
- Slow process indicates variation across the chip that can slow down the performance like slow operation of both pmos and nmos in a CMOS configuration.
- High temperature increases the resistance and low voltage (VDD) increases the charging time of output capacitance; both reducing the performance. Hence this slow corner is used for checking setup time along with any operating mode of the chip.
- Hold timing is also checked at this corner but most of the time it will be clean as hold is getting checked at slow corner.
- RC_best_fastProcess_LowTemp_HighVoltage: This scenario is generally used for checking hold time. RC_best indicates the best values of Resistance and best values for coupling and ground capacitance on interconnects are taken into the account ; fast process indicates variation across the chip that can speed up the process like fast operation of both pmos and nmos in a CMOS configuration.
- Low temperature reduces the resistance and high voltage (VDD) decreases the charging time of output capacitance; both speeding up the performance. Hence this fast corner is used for checking hold time along with any operating mode of the chip.
- Setup timing is also checked at this corner but most of the time it will be clean as setup is getting checked at fast corner.
- RC_worst_fastProcess_LowTemp_HighVoltage: This scenario is worst case check for power analysis. RC worst parasitic corner results in high power dissipation in interconnects, whereas fast process, low temperature and high voltage result in fast transition of the signal.
- Again, this corner can be used to analyze power at any functional mode.
DMSA
- Distributed Multi-Scenario Analysis (DMSA) can analyze timing and power in multi-scenario environment in parallel. To invoke prime time in DMSA, use multi_scenario option,
pt_shell ‘-multi_scenario’
- A single session gets open (called as master), along with different hosts(worker processes) which will be managed by master.
- User only communicates with master. Master allocates task to slaves, each one of which is dedicated to only one scenario. Number of worker processes (pt sessions) will be most of the time equal to the number of scenario.
- A scenario is a combination of operating condition (process, voltage, temperature) and operating mode (like functional mode, test mode). So, if there are 8 scenarios defined, then 8 worker processes will be launched which will be managed by single master.
- Dividing the data needed for multi-scenario timing analysis into common data and specific data, will speed up the process as certain data is common among all the scenarios like netlist and hence didn’t need to be defined separately for each scenario, and some data will be very specific for each scenario which will not be used by any other scenario like spefs.
DMSA ECO Fixes
1. Transition Time Fixing: Transition time can be fixed in 3 ways, i) swapping the cell to lower vts, ii) up-sizing the cell, iii) inserting buffer.
To avoid any area penalty i.e. to avoid up-sizing of cell or adding any buffer; swapping to lower vts is a safe option to fix transition time on the paths which are violated by less margin. Moreover, inserting a buffer may hamper the setup timing of that particular path. Following is the command used for fixing transition time,
fix_eco_drc -type max_transition -methods size_cell -setup_margin value
–hold_margin value
- The size_cell option in above command may up-size the driver cell also. In order to avoid this up-sizing, set PT variable eco_alternative_area_ratio_threshold to 1.0; as setting it to 1.0 will ensure that area of cell will remain same. Other method for fixing transition time is insert_buffer.
- If insert_buffer method is used to fix the transition time, then the list of buffers should also need to be mentioned that should be used during buffer insertion. We can also specify setup and hold margin so as to preserve both the timing parameter when fixing transition time.
2. Setup Time Fixing: The very basic step in fixing setup timing is to swaps higher vts to lower vts. Other fixes like up-sizing, cross-talk analysis can be done afterwards if the timing is not getting improved by swapping of the cell. Following is the command used for fixing setup time,
fix_eco_timing -methods size_cell -type setup -hold_margin value -slack_lesser_than value
- Setting PT variable eco_alternative_area_ratio_threshold to 1.0 will ensure that size_cell option in above command will prevent any area changes of a cell. If it is set to 2.0, it will allow to increase the cell area by 2 times the original area. Setting it to 0 will impose no restriction on area and tool may size it to any driver strength which is not recommendable.
3. Power Optimization: Cells in the timing path that have higher setup margin can be converted to higher vts, their driver strength can be reduced (downsizing) to optimize leakage and dynamic power, or extra redundant buffers can also be removed if it has enough setup and hold slack. Following is the command that is used for fixing power,
fix_eco_power -setup_margin value -pattern_priority [list …]
- When -pattern_priority is specified, tool will only swaps the lower vts to higher vts depending upon the priority given to VT cells, and will not do any downsizing. If -pattern_priority option is not specified than tool will downsize the cells to optimize the dynamic power.
4. Hold Time Fixing: Hold fixing can be done by either swapping lower vts to higher vts or by inserting buffers. For fixing hold using swapping, set the PT variable eco_alternative_area_ratio_threshold to 1.0. Following is the command for fixing the hold timing through swaps,
fix_eco_timing -type hold -methods size_cell -setup_margin value
-slack_lesser_than value
- -setup_margin option in the above command will make sure that the setup timing will be preserved by the value specified. If hold fix is to be done by buffer insertion than list of buffer need to be specified that are to be used during buffer insertion. Option -physical_mode will insert buffers by extracting cell placement information from lef and def. Following command for hold fixing is used,
fix_eco_timing -type hold -methods insert_buffer -setup_margin value -physical_mode mode -slack_lesser_than value