Qualcomm Physical Design Interview Questions and Answers

 1. Draw NAND/ NOR gate using CMOS?

2. What is tie-high and tie-low cells?

TIEH & TIEL cells are used to protect cells from ESD. cell input pins will get connected to TIEH/TIEL instead of connecting them to PG. If they are connected to directly to PG, cells are going to damage if there is a power supply fluctuation.

3. Explain Uncertainty? Why Uncertainty value is different for setup and Hold?

Uncertainty: It specifies a window within which a clock edge can occur. In physical design uncertainty will be used to model several factors like jitter (the deviation of clock edge from its ideal position), additional margins and skew (at pre-cts)

There will be different uncertainty values specified for setup and hold.

As hold check is performed with respect to same clock edge, any deviation in clock edge (jitter) will affect both launch and capture flop in same way.

So, for hold uncertainty no need to model jitter, this is the reason, why we always see less value for hold uncertainty compared to setup uncertainty.

Before CTS, uncertainty will also model the expected skew after implementation of clock tree (post-cts). So, at post-cts stages we will reduce the uncertainty values as actual skew values are available.

Setup Uncertainty:

• Pre-Cts = Jitter + Skew + Extra setup margin
• Cts = Jitter + Extra setup margin

Hold Uncertainty:

• Pre-Cts = Skew + Extra hold margin
• cts = Extra hold margin

4. How do you fix setup timing violation after base gets frozen?

• See if there are any detours on the nets in that path. Then remove re-route.
• Route on higher metal layer or layer promotion
• Fix crosstalk issue on data path
• Fix crosstalk issue on clock path
• Insert buffer by converting fortune /spare cells.
• Logic restructuring. I.e. re-arranging timing critical nets of AND gate away from its ground & timing critical nets of OR gate away from its power. So that non timing critical nets comes first & doesn’t acts as load for timing critical nets. Eventually delay will reduce

5. How to reduce Dynamic Power?

• Reduce switching activity by designing good RTL
• Clock gating
• Architectural improvements
• Reduce supply voltage
• Use multiple voltage domains-Multi vdd
• Reduce load or wire capacitance by minimizing the net lengths
• Use place.coarse.icg_auto_bound command to place registers close to its driver ICG o Improve transitions on the nets
• Use Decoupling Capacitors: It helps reduce power supply transients on the die and reduce dynamic or active power in the design, but it increases leakage power
• Use clock gating, xor self-gating, power gating and multibit flops for addressing dynamic power
• Area Recovery optimization: Downsize the drive strength of non-critical timing paths. So that their input pin cap will come down (CL is sum of wire cap, intrinsic capacitance of driver and input pin capacitances of fanout load). So dynamic power will reduce.
• The tool optimizes the dynamic power by minimizing the net length of high switching nets to improve the power QoR if we give SAIF file (It has static probability & toggle rates for each signal net in the design, sdc will have toggle rate & static probability of clock nets) based on gate level or RTL simulation (or by annotating set_switching_activity on the design in the absence of SAIF file) by enabling power_low_power_placement and set_dynamic_optimization
• Reduce unnecessary pessimism in setup/hold uncertainties (few people run a smaller number of timing scenarios by keeping huge uncertainty values) & use POCV (This will reduce the instance count and its internal short circuit power).

6. Why don’t you fix peak power in dynamic and why do u fix only RMS power?

In DC circuits the power is always calculated as the RMS power which produces the same heating effect as the DC power.

The current drawn is always the rms current …. I=sqrt(Power/Resistance)

7. What are all the contents present in .lib file?

a. Input capacitance
b. Leakage power under all condition
c. Functionality of the cell
d. Output transition in Look up table format
e. Cell delay table
f. Insertion delay table for macros [ always verify this in CTS stage]

8. What are all the contents present in .lef file?

a. SIZE
b. TILE
c. Symmetry
d. OBS
e. PIN BOX with layer
f. Origin

9. Explain about .sdc file

a. Import the Verilog in ICC
b. Get all the clock ports
c. Define clock on these ports
d. Run check_timing and clean the errors reported
e. Define IO cons

10. Explain about Useful Skew

a. Required whenever there is no scope of optimization on data path
b. Useful Skew on Launch path:

Many start points need to be early

Some cases difficult to make clock early as it may violate transition

Condition: +ve setup slack to launch register

c. Useful Skew on capture path:

Preferred as STA analysis is done based on endpoint and lesser endpoint count

 Increase the capture clock path delay

 Relatively easier to increase the clock delay

Condition: +ve setup slack from capture flop

11. What are all the things you will check, once placement gets completed?

Legality of cell placement

Timing

• Module placement
• Path by path

Congestion

• Congestion = (required tracks/available tracks)
• Required tracks: reduce cell density, pin density, cris-cross in cell signal routing because of wrong cells placement for the path
• Cell density: soft, partial, hard. Guide, region, fence, keep_out_margin

Density

• PIN DENSITY
• CELL DENSITY
  COND1: pin density is high and cell density is okay
• Keep_out_margin
  COND2: pin density is okay and cell density is high
• Soft, partial, hard
  COND3: pin and cell density both are high

12. What are all the outputs of Placement?

• Timing
• Congestion
• Design density
• Area
• Power

13. What is Banking and Debanking?

• Banking: combining the REGs into one STD cell
• DE-banking: separating the registers from bank
• It is also called flop trays.

14. What are all the checks after CTS?

a) Cells are legally placed
b) Cells used as per input given
c) Transition time on clock path
d) SKEW
e) Insertion delay
f) Timing
g) Congestion

15. How will you fix shorts and opens

a. Generally, tool will not leave any open.

• If there are any special attributes defined on that net (skip_route, freeze)
•  Reset these attribute and run commands (route_zrt_eco, ecoRoute)

b. Shorts:

• Shorts with cell internal blockage
• Move the cells if possible
• Or run eco router again with settings to tool can identify these shorts.

16. What is the difference you have observed in lower technology nodes?

Going down means from higher to lower technology node we facing the more complex challenges like

• Crosstalk
• More DRCs
• more Ir drop
• more Area reduced more congestion issue.
• Signal Em violation
• more Power dissipation more

17. Explain Positive, negative and Zero Slack?

The slack is the factor that determines the speed or frequency of the specific design. It is related to the timing path and can be calculated as:
Slack = Actual time-desired time

The negative slack means, there is some timing violation. The design has not achieved a specific speed or frequency.
The positive slack means, the design is achieving the specific speed or frequency. It has some extra margin as well.
The zero slack signifies that there is no margin, but the designer is already working on the exact speed or frequency.

18. What do you know about OCV?

All devices along a chip should run at a specific speed and interconnects should be either at the worst-case or best-case corner. But due to some variations at the manufacturing level, the speed is not uniform throughout the chip. There is variation in effective channel length and width of transistors. Due to complexities and variations in submicron technologies, the devices with the same size may have different width as compared to the idle condition.

The major on-chip variations are:

1. Variation in the channel length
2. Variation in temperature
3. IR drop variation
4. Variation in transistor width
5. Variation in threshold voltage
6. Variation in interconnects

19. Explain Clock Jitter

Clock jitter is the clock edge inaccuracy introduced by the clock signal generation circuitry w.r.t ideal clock. Clock jitter may be viewed as a statistical variation of the clock period or duty cycle.

Sources of clock jitter:

• Temporal power supply variations
  1. Changing activity can alter supply voltage in different cycles affecting either the global or regional (local) clock buffers.
• PLL Jitter
  1. Supply variation at PLL can affect oscillator frequency.
  2. PLL components do not have zero response time.
• Wire coupling
• Dynamic De Skewing Circuitry

20. Tell me about the advantages of Non-Default Rules (NDR)

1. By applying the double width we can avoid the EM.
2. By applying double spacing we can avoid the cross-talk.
3. Help’s to avoid congestion at lower metal layer.
4. Help’s pin accessibility of std-cells .