These files are the inputs for synthesis, floorplanning and are required for all the Physical Design stages.
CONTENTS OF .LIB
- The information inside the Lib file can be divided into two main parts.
- In the first part, it contains some information which is common for all the standard cells.
- The common part of Lib file contains : 1) Library name and technology name 2) Units (of time, power, voltage, current, resistance and capacitance) 3) Value of operating condition ( process, voltage and temperature) – Max, Min and Typical
- Cell delay is a function of input transition and output load and is calculated based on lookup tables.
- Cell delays are calculated by Nonlinear Delay Model(NLDM) and composite current source (CCS) models.
- Based on operating conditions there are three different lib files for Max, Min and Typical corner
- In the second part of Lib file, it contains cell-specific information for each cell. The part of Lib file which contains cell-specific information is shown below.
Cell-specific information in Lib file is mainly:
1) Cell name
2) PG Pin name
3) Area of cell
4) Leakage power in respect of input pins logic state
5) Pins details
CONTENTS OF LEF
- A LEF file is used by the router tool in PnR design to get the location of standard cells pins to route them properly.
- So it is basically the abstract form of layout of a standard cell.
- A LEF file describing the Library has mainly two parts.
1) Technology LEF
2) Cell LEF
.tech.lef (Cadence format)
.tf – technology file ( Synopsys format)
1) TECHNOLOGY FILE
- Technology LEF part contains the information regarding all the metal interconnects, via information and related design rules whereas cell LEF part contains information related to the geometry of each cell. A sample snapshot is given below to show the information under technology LEF part.
- Technology LEF part contains the following information
1) LEF Version ( like 5.7 or 5.8 )
2) Units (for database, time, resistance, capacitance)
3) Manufacturing grids
4) Design rules and other details of BEOL (Back End Of Layers)
- Layer name (like poly, contact, via1, metal1 etc)
- Layer type ( like routing, masterslice, cut etc)
- Preferred direction (like horizontal or vertical)
- Pitch
- Minimum width
- Spacing
- Sheet resistance
2) CELL LEF
- Cell LEF part contains the information related to each cell present in the standard cell library in separate sections.
- Cell LEF basically contains the following information
1) Cell name (like AND2X2, CLKBUF1 etc)
2) Class ( like CORE or PAD)
3) Origin 0 0
4) Size (width x height)
5) Symmetry ( like XY, X, Y etc)
6) Pin Information
- Pin name (like A, B, Y etc)
- Direction (like input, output, inout etc )
- Use (like Signal, clock, power etc)
- Shape (Abutment in case of power pin)
- Layer (like Metal1, Metal2 etc )
The rectangular coordinate of pin (llx lly urx ury).
Technology specific inputs
CONTENTS OF DEF
- DEF file is used to represent the Physical layout of an Integrated Circuit (IC) in ASCII format.
- A DEF file contains the design-specific information of the circuit and it is a representation of the design at any point during the physical design. DEF conveys logical design data and physical design data. Logical design data includes internal connectivity (represented by netlist), group information and physical constraints. Physical data includes placement location and orientation of components and routing geometry.
- A standard DEF file contains mainly following sections and order of statement is also important.
- [ VERSION statement ]
- [ DIVIDERCHAR statement ]
- [ BUSBITCHARS statement ]
- [ DESIGN statement ]
- [ TECHNOLOGY statement ]
- [ UNITS statements ]
- [ DIAAREA statement ]
- [ ROW statement ]
- [ TRACKS statement ]
- [ CELLGRID statement ]
- [ VIAS statements ]
- [ NONDEFAULTRULES statement ]
- [ COMPONENTS statement ]
- [ PINS section ]
- [ BLOCKAGE section ]
- [ FILLS section ]
- [ SPECIALNETS section ]
- [ NETS section ]
- [ SCANCHAINS section ]
- [ GROUPS section ]
- [ BEGINEXT section ]
- END DESIGN statement
Header statement:
ROW statement:
Track statement:
GCell Grid statement:
Via statement:
All vias consist of shapes on three Layers
1.A cut layer
2.Two routing (or masterslice) layers that connect through that cut layer
Component section
Pin section:
•It defines external pins
•Each pin definition assigns a pin name for the external pin and associates the pin name with a corresponding internal net name
•The pin name and the net name can be the same.
Blockage section:
•Defines placement and routing blockages in the design
•PUSHDOWN : Specifies that the blockage was pushed down into the block from the top level of the design
Net section:
