- Fabricating transistors is the very first step in IC fabrication which is generally known as Front End of Line (FEOL) .Then through metallization, these transistor gets connected on the wafer.
- When fabricating metal layers, first a particular metal layer is laid across the chip and then the unwanted part is etched away using plasma etching. This where process antenna rules plays a significant role. It’s a DFM check.
- During plasma etching, a high charge is induced on the layer that is being fabricated. Depending upon the area of the layer, this charge may get accumulated and discharges through gate oxide layer and damaging it as shown in fig(i); thus decreasing the yield of the chip.
fig(i) Process Antenna Effect
- If the area of the layer connected to the gate directly or connected to the gate through the lower layers is large compared to the area of the gate, then the static charges accumulated on that particular layer during plasma etching may get discharge through the gate resulting into damage of the oxide layer and permanent damaging of the transistor.
Antenna Ratio Checks
Antenna rules are defined in LEFs. These rules are different for metal layers and vias. Generally, either of the two checks are performed from the following,
- Cumulative Area Ratio Check (CAR): This check will take into the account the effects of the current layer in check along with the layer(s) that are beneath it i.e. from M1 layer up to the layer that is being checked.
- So, when calculating Antenna Ratio (metal area/gate area); metal area will be summation of the area of the current layer in check plus the area of the layer(s) beneath it; though most of the LEFs won’t combine metal area and cut area and hence most of the tool will not include via area when calculating antenna ratio on metal layer.
- Most of the LEFs are defined with the rules supported for this check. If the rules related to ANTENNA check in LEF is associated with keyword CUM (cumulative); than the LEF is defined with the CAR check.
- The tool will compare Cumulative Area Ratio (CAR) of metal layer with ANTENNACUMAREARATIO for the layer in check in LEF; and if the CAR exceeds this value, then a violation occurs.
- If a diode is attached with the gate, then CAR of metal layer will be compared to ANTENNACUMDIFFAREARATIO-this value will be larger than the ANTENNACUMAREARATIO as connecting a diffusion region(diode) to the gate will relax the antenna ratio.
- Alternatively, instead of specifying a single limit for antenna ratio, some LEFs specify a piece-wise linear (PWL) model of diffusion area and antenna ratio limit.
- Partial Area Ratio Check (PAR): This check considers only the current layer (single layer) area while calculating the antenna ratio. It neither consider the layers beneath the current layer nor the via area. When the number of total routing layers in a technology are less, this check is sufficient for calculating process antenna ratio.
Process Antenna Fixes
- Routing on Higher Metal Layer: A part of long interconnect can be taken to higher metal routing layer and back. This in known as metal jumping.
- This metal jumping is usually done near to the load. This metal jumping will break the long interconnect and hence the charge collected on the long interconnect will not discharge through gate oxide because the higher metal layer is not yet fabricated. This solution may increase the routing congestion on higher metal layers.
- Adding Dummy Load: Antenna Rule is the ratio of metal area to gate area. So increasing gate area will reduce the antenna ratio. Gate area can be increased by adding a dummy load (mostly inverter or buffer) and connecting the gate of dummy cell to the gate of the cell with high antenna ratio. Output of dummy cell is kept floating.
- Reduce the via-area: Large via area also results in process antenna violation. Converting multi-cut vias to double-cut via or double-cut vias to single-cut via reduces the cut area. Though it may impose serious reliability issues such as electromigration.
- Diode Insertion: Connecting a diode (diffusion) to the gate electrode (load) provides a discharging path for the static charge present on the metal layer (antenna) as shown in fig (ii). Diode should always be connected in reverse bias, with cathode (diffusion) connected to gate electrode and anode (substrate) connected to ground potential.
- Generally, avalanche diode is preferred due to its capability of withstanding high voltage in reverse bias. So, when plasma etching induces negative charges, avalanche diode works in forward bias shunting all the current to ground and when plasma induce positive charges, diode works in reverse-bias mode and avalanche breakdown occurs due to high voltage across it and hence allowing high current to pass through it.
- Generally, other diodes (pn diode, Zener diode etc) suffers a permanent failure once breakdown occurs but avalanche diodes are designed (less doping concentration) to break down at a high reverse voltage without getting damaged.
- Insertion of diode doesn’t affect the normal operation as normal operation works at very low voltage that is not capable of causing an avalanche breakdown.
fig(ii) Diode Insertion
- Automatic Fixes: Clock pins are highly susceptible to antenna violation as most of layers in clock net are wide(NDR) and vias are also large in terms of area(multi-cut/NDR-via).
- So, most of the PnR tool inserts diode automatically on the pins with high antenna ratio. Though inserting diodes has it own demerits.
- Firstly, adding high number of diodes will occupy more space that are reserved for standard cells to place; they dissipate heat (leakage power) and lastly, they increase the diffusion capacitance seen by driver pin which will impact the performance.
- Alternatively, most of the routing engine can be instructed to go for metal hopping/jumping to solve antenna violation and avoid diode insertion.