SDC Constraint files are given to the tool at each stage of the Physical Design flow
i.e) Synthesis, Placement, CTS, Routing
create_clock-name clk -period 2.22 -waveform {0 1.11} [get_ports clk]
➢ We should provide the clock constraints to all the clk ports in the design.
create_generated_clock-multiply_by 2 -name ckGen2x-source clk [get_pins ckGen/U8/Z]
➢ If there is any pins which has the source clk input we should create generated clk
set_clock_uncertainty 0.4 [get_clock clk]
➢ We are setting 20% of clk period as clock uncertainty which is an ideal case. We took it as the limit
for the possible deviation of the clk edge from its ideal location.
set_clock_latency-source 0.2 clk
➢ We are setting insertion delay from clock source to clock definition point as 10% of clock period.
set_clock_latency 0.2 clk
➢ Similarly, we are setting insertion delay from clock port to clk sink point of sequential elements as
10%.
set_input_delay 1.33 [all_inputs] -clock clk
➢ We are setting input delay as 60% of clk period for every register to input port paths.
set_output_delay 1.33 [all_outputs] -clock clk
➢ Similarly, we are setting output delay as 60% for every output port to register paths.
❖ For feed through paths the delay is considered as 30% ideal case, otherwise we get input from full
chip level.
set x [filter [all_fanout -from [all_inputs]] “port_direction == out”]
➢ We are filtering out feed through paths from input to output and taking output ports as a list.
set y [filter [all_fanin -to [all_outputs]] “port_direction == in”]
➢ We are filtering out feed through paths from output to input and taking input ports as a list.
set_input_delay 0.77 [get_ports $y] -clock clk
➢ We are setting input delay as 35% for every register to input port paths.
set_output_delay 0.77 [get_ports $x] -clock clk
➢ We are setting output delay as 35% for every output port to register paths.
❖ We are creating four group paths and checking whether the timing constraints have been met or
not.
group_path-name i2o -from [all_inputs] -to [all_outputs]
group_path-name i2r -from [all_inputs] -to [all_registers]
group_path -name r2r -from [all_registers] -to [all_registers]
group_path-name r2o -from [all_registers] -to [all_outputs
Timing Exceptions
Timing exceptions allow you to modify the default timing analysis rules for specific paths, such as
multicycle paths, false paths, and minimum and maximum delays.
- set_false_path
- set_multicycle_path
- set_max_delay
- set_min_delay
SDC Commands related to timing
report_transitive_fanout-from spi_clk
➢ This command reports the information of the full path with which this clk port is connected.
set_false_path-from [get_ports spi_clk] -to [get_pins spi_slave0/spi_clk_q_reg/D]
➢ A falsepath is a path existing in a design which should not be analyzed for timing.
➢ If there are two different clocks which are not synchronized and a path between two multiplexed
blocks that are never enabled at the same time etc couldn’t meet the setup slack.
set_multicycle_path 2 -from [get_pins REGc/regout_reg[1]/CP]-to [get_pins MUL1/q_reg[12]/CP ] -setup
➢ Inthis step we are creating a multicycle for reliable capture of required data by setting the number
of clock cycles in a path.
set_max_delay
➢ With this command we can set more time to the path which is violating.
Set_min_delay
➢ This command is mainly for hold operation, we can set minimum delay to particular path.
set_driving_cell-library tcbn28hpcplusbwp30p140hvtssg0p72vm40c_ccs-lib_cell
BUFFD0BWP30P140HVT [remove_from_collection [all_inputs ] clk]
➢ If we don’t set the drive strength for input ports, there is no limit in driving by input ports which
cause the delay in the cells due to high transition time and load, it leads to violation in setup slack.
set_max_capacitance 2 [all_outputs]
➢ Similarly, as in case of output ports it is not defined to limit HFNS, which leads to increase in delay.
set_max_area 0
➢ We are setting max area to zero, so that the tools tries to use as minimum area as possible.