What is STA
Static Timing Analysis is a technique of analysing timing paths in a digital logic by
adding up delays along a timing path (both gate and interconnect) and comparing it
with constraints (clock period) to check whether the path meets the constraint.
In contrast to the dynamic spice simulation of whole design, static timing analysis
performs a worst-case analysis using very simple models of device and wire delays. A
lookup table model or a simple constant current or voltage source-based model of
device is used.
Elmore delay or equivalent model is used to quickly figure out wire
delays.
Static Timing Analysis is popular because it is simple to use and only needs
commonly available inputs like technology library, netlist, constraints, and
parasitics (R and C).
Static Timing Analysis is comprehensive and provides a very high level of timing
coverage. It also honors timing exception to exclude the paths that are either not true
path are not exercised in an actual design.
A good static timing tool correlate well
with actual silicon
What is Timing Path in STA
For standard cell based designs, following figure illustrates basic timing path. Timing
path typically starts at one of the sequential (storage element) which could be either a
flip-flop or a latch.
The timing path starts at the clock pin of the flip-flop/latch. Active clock edge on this
element triggers the data at the output of such element to change. This is the first stage
delay which is also called clock -> data out(Q) delay.
Then data goes through stages of combinational delay and interconnect wires. Each of
such stage has its own timing delay that accumulates along the path. Eventually the
data arrives at the sampling storage element, which is again a flip-flop or a latch.
That’s where data has to meet setup and hold checks against the clock of the receiving
flip-flop/latch. Also notice for the timing paths in the same clock domain, generating
flip-flop clock and sampling flip-flop clocks are derived from a single source, which is
called the point of divergence.
In reality, actual start point for a synchronous clock based circuits is the first instance
where clocks branch off to generating path and sampling path as shown here in the
picture, which is also called point of divergence.
To simplify analysis, we agree that clock will arrive at very much a fixed time at the
clock pin of all sequential in the design. This simplified the analysis of the timing
path. from one sequential to another sequential.
Items that are checked by Static Timing Analysis
Static Timing Analysis is used to check mainly the setup and hold time checks. But it
also checks for the assumptions made during timing analysis to be holding true.
Mainly it checks for cells to be within the library characterization range for input
slope, output load capacitance. It also checks for integrity of clock signal and clock
waveform to guarantee the assumptions made regarding the clock waveforms.
9 STA checks
Setup Timing
Hold timing
Removal and Recovery Timing on resets
Clock gating checks
Min max transition times
Min/max fanout
Max capacitance
Max/min timing between two points on a segment of timing path.
Latch Time Borrowing
Clock pulse width requirements
7 Different types of Timing Paths in STA
i. A path between the clock pin of register/latch to the d-pin of
another register/latch.
ii. A path between primary input to the d-pin of a register or latch.
iii. A path between clock-pin of a register to a primary output.
iv. A timing path from primary input to macro input pin.
v. A timing path from macro output pin to primary output pin.
vi. A timing path from a macro output pin to another macro input
pin(not shown in the figure)
vii. A path passing through input pin and output pin of a block
through combinational logic inside the block