Source Delay (or Source Latency)
- It is known as source latency also. It is defined as “the delay from the clock origin point
to the clock definition point in the design”. - Delay from clock source to beginning of clock tree (i.e. clock definition point).
- The time a clock signal takes to propagate from its ideal waveform origin point to the
clock definition point in the design.
Network Delay(latency)
- It is also known as Insertion delay or Network latency. It is defined as “the delay from the
clock definition point to the clock pin of the register”. - The time clock signal (rise or fall) takes to propagate from the clock definition point to a
register clock pin.
Insertion delay
The delay from the clock definition point to the clock pin of the register.
Transition delay
It is also known as “Slew”. It is defined as the time taken to change the state of the signal.
Time taken for the transition from logic 0 to logic 1 and vice versa . or Time taken by the
input signal to rise from 10%(20%) to the 90%(80%) and vice versa.
Transition is the time it takes for the pin to change state
Slew
Rate of change of logic. See Transition delay.
Slew rate is the speed of transition measured in volt / ns.
Rise Time
- Rise time is the difference between the time when the signal crosses a low threshold to
the time when the signal crosses the high threshold. It can be absolute or percent. - Low and high thresholds are fixed voltage levels around the mid voltage level or it can be
either 10% and 90% respectively or 20% and 80% respectively. The percent levels are
converted to absolute voltage levels at the time of measurement by calculating
percentages from the difference between the starting voltage level and the final settled
voltage level.
Fall Time
- Fall time is the difference between the time when the signal crosses a high threshold to
the time when the signal crosses the low threshold. - The low and high thresholds are fixed voltage levels around the mid voltage level or it
can be either 10% and 90% respectively or 20% and 80% respectively. The percent levels
are converted to absolute voltage levels at the time of measurement by calculating
percentages from the difference between the starting voltage level and the final settled
voltage level. - For an ideal square wave with 50% duty cycle, the rise time will be 0.For a symmetric
triangular wave, this is reduced to just 50%.
Absolute Rise Time
In absolute rise time, the low and high thresholds are fixed voltage levels around the mid
voltage level.
Percent Rise Time
In percent rise time, the low and high thresholds are percent levels, and are usually either
10% and 90% respectively or 20% and 80% respectively. The percent levels are
converted to absolute voltage levels at the time of measurement by calculating
percentages from the difference between the starting voltage level and the final settled
voltage level.
Definition of Fall Time
Fall time is the difference between the time when the signal crosses a high threshold to
the time when the signal crosses the low threshold. It can be absolute or percent.
Absolute Fall Time
In absolute fall time, the low and high thresholds are fixed voltage levels around the mid
voltage level.
Percent Fall Time
In percent fall time, the low and high thresholds are percent levels, and are usually either
10% and 90% respectively or 20% and 80% respectively. The percent levels are
converted to absolute voltage levels at the time of measurement by calculating
percentages from the difference between the starting voltage level and the final settled
voltage level.
Significance of Rise Time & Fall Time
This is best explained by comparing a square wave with a triangular wave. In an ideal
square wave with 50% duty cycle, the rise time will be 0 and the signal will be above
threshold for 100% of the half period time.
In a symmetric triangular wave, this is reduced to just 50%. More severely affected is the total area above the threshold, which is reduced to 25% of that of square waves.
Though the information about loss of time above threshold is conveyed by many other parameters, the information about loss of area above threshold is only conveyed by rise and fall times.
Rise Time & Fall Time Requirements
The rise time & fall time should be small compared to the clock period. A factor of 10 is
considered good. Very large rise or fall times have the risk of the cycles going undetected.
Also, large rise or fall times mean that the signal will be hovering around mid level for too long, making the system highly susceptible to noise and multiple triggering if there is not enough hysteresis.
This might make you think that the faster rise & fall times are, the better the system is.
Not really. Very fast rise or fall times are not free from trouble.
They might cause severe ringing at the receiver resulting in reduction in voltage & timing margins or even double triggering. Or the fast edges can & will get coupled to the adjacent signal lines causing
false triggering on them or reducing the voltage margins.
Path delay
Path delay is also known as pin-to-pin delay. It is the delay from the input pin of the cell
to the output pin of the cell.
Net Delay (or wire delay)
- The difference between the time a signal is first applied to the net and the time it reaches
other devices connected to that net. - It is due to the finite resistance and capacitance of the net.It is also known as wire delay.
- Wire delay =fn(Rnet , Cnet+Cpin)
Propagation delay
- For any gate it is measured between 50% of input transition to the corresponding 50% of
output transition. - This is the time required for a signal to propagate through a gate or net. For gates it is the
time it takes for a event at the gate input to affect the gate output. - For net it is the delay between the time a signal is first applied to the net and the time it
reaches other devices connected to that net. - It is taken as the average of rise time and fall time i.e. Tpd= (Tphl+Tplh)/2.
Intrinsic delay
- Intrinsic delay is the delay internal to the gate. Input pin of the cell to output pin of the
cell. - It is defined as the delay between an input and output pair of a cell, when a near zero slew
is applied to the input pin and the output does not see any load condition.It is
predominantly caused by the internal capacitance associated with its transistor. - This delay is largely independent of the size of the transistors forming the gate because
increasing size of transistors increase internal capacitors.
Extrinsic delay
- Same as wire delay, net delay, interconnect delay, flight time.
- Extrinsic delay is the delay effect that associated to with interconnect. output pin of the
cell to the input pin of the next cell.
Input delay
- Input delay is the time at which the data arrives at the input pin of the block from external
circuit with respect to reference clock.
Output delay
- Output delay is time required by the external circuit before which the data has to arrive at
the output pin of the block with respect to reference clock.