Uncertainty in Physical Design

How uncertainty is estimated at each stages of Physical Design?

1. The “Uncertainty” is a state of estimating unknown about the future. If we estimate accurately in present, the future will be amazing.
2. Here are some major points to estimate the uncertainty from Synthesis (present) to Sign-off (future) based VLSI flow.

* Frequency

* Technology

* Latency

* Jitter

* Skew

* OCV

* Cross Talk

* PVT variations

• Frequency: The frequency is affected by physical parameters like temperature, noise and some internal disturbances which leads to changes in the timing. So, it’s good to estimate the effects and decide the frequency for design.
• Technology: As the technology changes from one node to another node, the delay also changes but the effect of leakage increases as technology shrinks to lower node which affects the delay and device reliability. So, not all uncertainty values are suitable for all nodes, it depends on node and also change.
• Latency: The latency is the delay in the clock path especially, this will come accurately as the design goes near to tape out and it depends on the OCV, Crosstalk, Metal & Technology etc.
• Jitter: The jitter is an unexcepted phenomenon which changes the frequency of PLL clock period from 5-10 % tolerance in industry. Estimate the uncertainty by including jitter value which gives better results in the design.
• Skew: The difference in launch latency and capture latency. The skew is not real from synthesis to placement due to idle clock. After in post-cts, the real clock propagates through metal layer and some physical parameters are also included which gives exact value. The skew estimation depends on the design, technology and derate values.
• Crosstalk: Crosstalk is a phenomenon that happens when two wires are placed near to each other and leads to crosstalk delay. The estimation of crosstalk delay will be on technology and frequency.
• PVT variations: The PVT variations are estimated by the fabrication team and provide different kinds of libraries helps for design to works in different PVT conditions. Validation is happening with different corners of libraries and depends on technology also.

1. Approximate estimation of uncertainty from RTL to GDS in VLSI Design flow.

• Logical Synthesis: At synthesis stage the clock, jitter, skew, OCV, PVT and crosstalk are idle only frequency & one technology node setup check. So here,

*Func(uncertainty_estimation) = Σ (estimated clock, jitter, skew, OCV, PVT, latency & crosstalk etc.)

• Post-Placement: The real cell placement with worst-case & best case PVT libraries which gives bit approximate value of uncertainty by considering the PVT variations.

*Func(uncertanity_calculated) = PVT variations and clock

*Func(uncertanity_estimate) = Σ (jitter, latency, skew, OCV & crosstalk)

• Post-CTS: The Post-CTS stage has a real clock with skew, jitter & OCV.

*Func(Uncertanity_calculated) = Σ ( Clock, jitter, skew, latency, OCV, parasitic of clock net)

*Func(Uncertanity_estimation) = crosstalk (design depends) and parasitic of signal nets

• Post-Route: The Post-Route has a real net, cell placement & propagated clock. The uncertainty gives accurate value as then above stages. It could approximately 15-20% of estimated values from synthesis.

*Func(uncertanity_calculated) = Σ (parasitic, crosstalk )

• Sign-off: The data from the above stages is accurate and easy to calculate the uncertainty by following the DRC rules.

Let me know if any other parameters help to estimate the uncertainty.