Questions 21 to 40
Physical design questions with answers
21. How die and core determined?
die size = core size + pad height + power ring width.
22. How insertion delay increases so jitter will be increase?
As insertion delay increases, The gates(buffers/inverters) increase resulting in process variations in the clock path which can affect the jitter.
23. Difference between gate count and instance count
The instance count is the actual number of standard cells in your design, and as you said, the gate count is the equivalent number of two-input nand gates that would occupy the standard cell area of your design.
Instance count always increase in PnR flow because adding buffers, physical cells etc and gate count remains same.
24. How will fix hold?
•For hold fixing will downsizing the cells or buffers and If it is LVT or HVT will swipe to HVT or LVT.
•We will insert the delay buffers in the data path.
25. What is NDR rules why we use?
NDR (Non-Default Rules) are
•Double width: Use to avoid the EM violation
•Double Spacing: Use to avoid the cross talk
•Shielding: It also some time we use for avoiding the cross talk
•We use NDR rule for clock nets because clock signals having very switching activity because of that we use the NDR rule
26. How to fix timing violation before CTS (Means in placement)?
Timing violation will be fixing by:
•Magnet placement
•By creating the bound
•Path grouping
27. NDR Preset in which file?
•NDR are present in the clock spec file.
•Because in CTS stage we applied NDR rules in clock nets only that’s why.
28. PNET violation:
PNET is nothing but the cells which are sits under the power strips that is PNET violation.
29. what will happen If cells is sits under power strips?
That cells will not get power, cells will not connect to the vdd vss, that’s why will see the pnet violation.
30. What is via? Why do we use it?
A via is an electrical connection that establishes the connectivity between two layers. Vias are established at points where a net changes layer.