Physical Design Interview Questions and Answers

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VLSI Physical Design Interview Questions with Answers

  1. If we are getting 20ps violation in 1 path, how will we fix it?  

First will select that pin or cell then will check the net length of that pin or cell if net length is more then 50micron then will break the net and will be adding the buffers.

If net length is less, then 50 then will check the driver size if it will be less then will up sizing.

If driver size is also good then will swipe up HVT to LVT, if this will also okay then will check the fan-out if fan-out is more then will split fan-out like this I will fix.

2. If I want to fix DRV’s 1000 max trans is violating then how will we fix in 1 or 2 shot?

I will take all the nets and then have to write script for that.

Ex: get_attribute [get_nets].

If the net length of the pin is less, then 50 microns, will add buffer near to the violating pin.

If the net length is more then 50 macron and less then 100 microns, will break the net and will add the buffer in the middle then it will drive.

If the net length is more then 100 microns, then will add the buffers after 60m or 70m whatever we want every 60 microns, will add the buffers.

Physical Design questions with answers

 3. If the add buffer in route if the one macro pin is there that macro pin is connect to another macro pin or cell that rout is going on top of the macro so will add the buffers?


If will add buffer in rout it will not take because the route start travelling of the top of the macro it will not do. That time will take the location (Coordinates) and will add the buffer.

4. If 1000 data trans, 1000 data caps, 1000 clock trans and some of the bad nets(Having length more) those are 500 so these three are violating so will fix these?

We need to take all this things in a single ECO

The net violating in data trans that same net can be violating clocks trans and same net may be bad net also so, I will take two files, one is related to clock , one is related to data. Whatever the data cap, data transition,bad nets or fan-out are there will put those nets in a single file, then will do the sorted means if the double-double nets is coming that will go

Then will give that command like nets less then 50microns, add buffer near to the violating pin….

same thing we will do in clock related things, take (clock trans, clock cap etc.) in one single file and will give that command like nets less then 50microns, then add buffer near to the violating pin.

5. If we are getting cross-talk issue (like 100 paths are there causing our setup) so how will we fix it?

In the victim net I will add the buffer if the net length is more, will break the net and will add the buffer.

For the victim net I will upsize the driver

I will swap the victim net

In some cases, I will aggressor nets downsize but at that time will check due to that any violation should not come then will do otherwise will not do anything with aggressor nets.

Will apply NDR rule like double spacing

By shielding will reduce cross talk

PD Interview QA

6.  what happens if we do the over keep-out margin?


If we give over key-pout margin we see the congestion in another place.
Our utilization will also jump.
For every keep-out margin utilization will jump.

7. What is multi-bit register?

Multi-bit resistor is nothing but number of flops will club together because of area optimization, timing optimization also, so will club it and give it as a multi-bit resistor. It will come in to picture only for the flip-flop.

8. What is magnet placement?

Magnet placement is nothing, but it will pull the cells nearby that, it will pull on logical level (logical depth & logical Div) that is called logical placement.

9. Where we use hard blockage and why?

Will use hard blockage to avoid the congestion

Will use on notches whenever we will see the notches

Will apply hard blockage there because if the cells are sitting in notches so the routing will we happen in crisscross to avoid that will block with help of hard blockages so nothing will sit in that area. 

10. How global routing will handle congested path?


Global routing is nothing, but it will divide whole blocks into sub blocks(G-cells)
But in placement stage global route will not happen, it will be virtual routing itself.
Global routing will not come into placement.

Because the congestion will only come in placement stage in routing only will see the shorts because the actual route will come.

If our congestion is good in placement will not see the shorts, if our placement is bad then will see the shorts in routing.

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