Questions 41 to 60
VLSI PD Interview QA
41. How will you reduce skew and insertion delay?
•First of all bad skew due to bad clock net routing issue, bad transition in few clock nets, physical constrains like Blockages, clock structure, incorrect clock buffers or invertors is used.
Bad clock routing:
Generally, the routing issue is considered when the skew is really a large and unacceptable number. In this case check for the route guide definition, redefine it to cover the clock pins.
Bad Transition:
The higher value of transition generally leads to a higher delay, thereby affecting the skew. Check if don’t touch and don’t size options are set for the cells. Then resetting the option of critical cells helps reducing the skew.
Physical Constraints:
The usage of placement blockages and their location must be optimal like between the macros(partial or soft blockages). Make sure the standard cell area in a block is rectangular in shape for optimal H-Tree clock structure formation.
Clock Structure:
Clock gates and their structures should be optimized in prior as gated clock might affect the overall clock structure.
The number of clock tree levels should not be too high. As the number of clock tree levels increase, it becomes difficult to balance the skew.
Uneven clock structure like wide fanout, flipflops of unequal drive strength etc
Incorrect buffers and inverters in clock tree:
Use correct buffers and inverters with correct driving strength, cell delay values and has to be specified prior to CTS.
42. Why LVT cells having more leakage power ?
•The LVT cells having more leakage power because the thickness of the gate oxide is less for LVT cells , so the gate tunnelling current will be more causing more current to flow through the gate.
43. What are challenges in clock gating ??
Few are below which I can think of
•Circuit timing changes.
•Area penalty (additional logic is added).
•Equivalency checking (especially for sequential clock gating).
•Clock domain crossing issues.
•Reset domain crossing issues.
•Complicate timing closure due to additional delay at clock network.
44. What is the difference between Create clock and Generated clock ??
There are few difference between CC and GC:
Create_clock command is used to define primary clock and virtual clock where
The create_generated_clock command is used to create a generated clock inside the design.
We can use create_clock command also for defining the secondary clocks generated in the design.
•Create_generated_clock definitely needed the primary clock source which is to be defined by the create_clock.
•Create_generated_clock definitely need to provide the fixed relationship between primary and secondary clocks.
•In create clock we define clock period, waveform, clock name, clock port name whereas in generated clock we define clock name, clock source, clock period we do not define waveform in generated clock.
•Command for create clock :
Create_clock -name CLK -period 10 -waveform {0,5} [get_ports clk]
•Command for generated clock:
Create_generated_clock -name gen_clk -source [get_clocks CLK] -divided_by 2 [get_pins gen_clk]
name – generated clock
Source – source of clock name (primary clock)
divide_by – frequency divided by value [get_pins gen_clk] is the pins of the generated clock.
45. What is clock jitter?
•Clock jitter describes how uniform the clock edges are in a digital signal. Clock jitter will influence the skew of a clock over time. If the clock is supposed to have an edge every millisecond (500hrz) but they fall between .9 and 1.1 milliseconds this would be the jitter. This is a sporadic deviation for the specific clock
46. Why u require uncertainity before cts with ideal clock?
•At the pre cts uncertainity is the combination of skew, jitter and margin.
To get the better time pre cts we required uncertainity.
47. Given two configuration of Vdd and Vss 1. VDD VDD VSS VSS 2. VDD VSS VDD VSS……….which configuration you have used and what does the tool prefer?
•Vdd vss because alternative (VDD VSS) will offer better routing resources.
48. What are retention registers?
•Retention flops are used in power gating.
•To retain the position of the off block when it is turned in.
49. What are HVT cells, how area increases with HVT cells?
•For HVT cells the oxide thickness under gate is very high. Such that it can reduces the leakage current. (as oxide thickness increases little area increases).
50. What are types of macros?
There are 3 types of macros.
• Hard macro
• Soft macro
•Firm macro
•Hard macro : Hard macros are defined in the LEF or GDS file. This macros are always come in terms of hardware IPs. While placing the hard macros we can move, rotate, flip but we can not change the functionality of the hard macros.
•Soft macro: Soft macros are defined in the synthesised RTL file. This macros are not depends on any technology, we can change the functionality of the soft macro.
•Firm macros: These macros are defined in the netlist.