• Smallest Half -Pitch of contacted Metal 1 lines [lowest metal in that process] that can be feasible/allowed in the fabrication process.  VLSI fabs, companies use this term as a parameter to measure/denote the advancement in fabrication process.
• Smaller the node –> denser the devices –> more computing logic in less area –> more functionality –> faster and lower power per function
• Important thing to note here is : Let’s say 16nm processor, should have half metal1 pitch as 16nm, but that’s not always the case at lower/advanced nodes: Companies are started calling approx. numbers as per marketing mantra. It does not correspond to any gate length or half pitch. But it’s almost around the quoted number

• Concept was raised previously due to the denser memory requirements [DRAM]. Since denser memories are dependent of process scaling, ITRS came up with initial metric to direct the technology advancement.
• Still this number is more a process name than the actual measure of any exact physical feature
• Two ways of looking at technology node concept:
  • If we are talking about mobile SoC/PCs etc.. : technology node is the half pitch between two adjacent DRAM metal lines. Now this doesn’t correspond with the Lmin of a MOS transistor and so you have to take this definition with a pinch of salt. For example, when a company focused on digital applications says its working on 17 nm technology, then it most probably means this DRAM half pitch, as that is the minimum feature size that can be “printed” by the lithography technique adopted by that company (which of course is less than the transistor Lmin in this case).
  • If we are talking about Analog Mixed signal applications: Where they employ BCD processes (Bipolar DMOS, CMOS) the book definition is not applicable.
  • So, if a person from such a company says he/she is working on 130 nm node for example, then it might not mean that the DRAM half pitch is 130 nm as they might not be using DRAMs at all! In such cases it can be safely assumed that the 130 nm is the Lmin of the MOSFET’s used in the process.
  • Initial definition: Smallest feature was almost always the line that defined the gate electrode on the MOS transistor. So the name of a process became identified with the width of the gate electrode.Just to make matters more complex, designers referred to this as the “gate length.” (If you look at a transistor the way the current does, from one end through to the other, the width of the gate electrode determines the path length the current must traverse getting through the channel region.)
  • Unfortunately for clarity, the gate length is also an approximate measure of transistor speed and of how densely you can pack transistors together in a hand-crafted layout.

• Marketing departments seized upon the term as a measure of goodness, and quickly turned what had been a measure of a physical dimension into a measure of marketing bravado. The result was that by about 350 nm (actually called 0.35 micron in those days), the “350 nm” had become simply the name of the process rather than a measure of any physical dimension.
• The process might only be able to resolve a 380-nm line width, but through various other tricks, process engineers could get the transistors to behave as if their channel length were 350 nm. So it goes.
• Today, the number has recovered some accuracy as a physical measure. A 65-nm process usually does have features—again, usually gate line widths—that are approximately 65 nm.
• There are exceptions. For instance, a company might design a process that will eventually be able to produce 65-nm lines, but for economic reasons they will leave out one or two critical pieces of equipment that would be necessary for the finest possible lines. They will usually announce this as a “65-nm” process, even though today it can’t do 65-nm features.
• The fascinating part today is that it is physically impossible for the printers, which work with 193-nm-wavelength light, to accurately transfer a 65-nm line from the mask to the wafer’s surface. So designers use incredibly sophisticated tricks to make patterns on the mask that, when blurred and distorted by diffraction in the printing process, will end up being sort-of credible 65-nm-wide lines. These tricks include attaching “decorations” all over the line on the mask—bulges in the center, little whiskers at the corners, things that make a rectangle look more like an image in an ink-blot test.
• This in turn means that even if you can make one perfectly acceptable 65-nm-wide line, you may not be able to make another one right next to it. You may have to leave room for decorations in between. So today, “65 nm” or “45 nm” doesn’t exactly refer to the line width, and certainly doesn’t indicate how closely you can pack transistors together, although it does provide some indication of these things. Still, it is probably most accurate to say that the number is simply the name of the process, rather than the measure of any particular feature

The post Technology Node appeared first on Learn VLSI.

DFT is the acronym for Design for Testability. DFT is an important branch of VLSI design and in crude terms, it involves putting up a test structure on the chip itself to later assist while testing the device for various defects before shipping the part to the customer.

Have you ever wondered how the size of electronic devices is shrinking? Mobile phone used to be big and heavy with basic minimal features back in 90s.

But nowadays, we have sleek phones, lighter in weight and with all sorts of features from camera, bluetooth, music player and not to forget with faster processors.

All that’s possible because of the scaling of technology nodes. Technology node refers to the channel length of the transistors which form the constituents of your device. Well, we are moving to reduced channel lengths. Some companies are working on technology nodes as small as 18nm. Smaller is the channel length, more difficult it is for the foundries to manufacture. And more are the chances of manufacturing faults.

Possible manufacturing faults are: Opens and shorts.

The figure shows two metal lines one of which got “open” while other got “shorted”. As we are moving to lower technology nodes, not only the device size is shrinking but that also enables to pack more transistors on the same chip and hence density is increasing. And manufacturing faults have become therefore indispensable. DFT techniques enable us to test these (other kinds as well) faults.

Kinds of defects:

• Opens and shorts, as mentioned above, can cause functional failures. A kind of open and shorts, where any node might get shorted to ground is referred to as stuck-at-0 (SA0) fault or in cases where the node might get shorted to the power supply is referred to as stuck-at-1 (SA1) fault.
• Speed Defect: May arise due to coupling of a net with the adjacent net and hence affecting the signal transition on it.
• Leakage Defect: Where a path might exist between the power supply and ground and this would cause excessive leakage power dissipation in the device.

DFT Modes: Perspective

As more number of transistors are finding their way onto a single SoC, Design for Testability (DFT) is becoming an increasing important function of the SoC design cycle.

As the technology nodes are shrinking consistently, the probability of the occurrence of the faults is also increasing which makes DFT an indispensable function for modern sub-micron SoCs.

What are the possible faults within an SoC and whhat all ways are possible to detect them? We will take them up briefly.

Imagine that you own a chip manufacturing company for the automotive industry. The end application can be something meant for infotainment, engine management, rear view camera, ethernet connectivity, power  glasses or for a critical application like collision detector or air-bag control etc. You wouldn’t like to sell a faulty chip to your customers for two main reasons:

• Trust of the customer which would impact the goodwill of the company.
• Loss of business: Maybe because the customer opted for some other semiconductor vendor or even worse, the chip failed at the user end and he sued your customer who ultimately sued you!

Hence, it is pretty important to test the chip before shipping it out to the customers.

Types of fault and their detection:

• Structural Fault: Basically refers to the faults due to faulty manufacturing at the fabs. Even a tiny dust particle has cause shorts or opens in an SoC. 
  Let’s try to understand it from our example. Let’s say you manufactured the chip but there is a fair probability  that there might be some structural inadequacies in the form of shorts or opens.
• Imagine any digital circuit. Single short or a single open can cause the entire functionality of the device to go haywire. Structural testing is done during the DFT tests or modes called as Shift and Stuck-At Capture. We’ll discuss these in detail in the upcoming posts. Note that these tests are conducted after manufacturing, before shipping the part to the customer.
• Transition Faults: Signal transitions are nothing but the voltage levels while they switch from either ‘high’ to ‘low’ or vice-versa. There is a designated time before the clock edge when all the signals should be stable at the input of the Flop (a very crude definition of setup time) and also a designated time after the clock edge when none of the signals should change their states at the input of the Flop (a very crude definition of hold time). Any such fault in the transition times (conversely: setup or hold violations) is referred to as a transition fault.
• Going back to our example. Suppose that you first filtered out the chips which had some structural fault. Now you would test the remaining chips for transition faults. What would happen if you ship a chip with a transition fault to a customer? If it had a setup violation, the chip will not be able to work at the specified frequency.
• However, it will be able to work at a slower frequency. If it had a hold violation, the chip will not be able to work at all! One possible consequence from our example could be that in an event of a collision you would expect a few micro- or nano- seconds for the air bag to open up, it might ending up taking seconds! Unfortunately, it would be too late.
  
• The At-Speed test is used to screen the chip for transition faults.
  Broadly speaking, there are only two types of the faults as discussed above. However, there’s another possibility which can arise. 
  Imagine that your car has an SoC which senses a collision and opens the  air bag  within a few micro-seconds of the collision. You would expect it to open up if such a scenario arises.
• But what if your car is, let’s say, 6 years old and the chip is now not functioning as expected. In this case, you would like to test the chip first. And if it is fine, you may proceed on to ignite the engine and start the car. Such a scenario would demand conducting a test while the chip is in operation.
• Such a DFT test is called LBIST Test (Logical-Built-in-Self Test). In an LBIST test, one would be testing the entire chip or a sub-part of it for structural and/or transition faults. Such a test for memory is referred to as MBIST Test (Memory-Built-in-Self-Test).
  
  An important characteristic of a built in self test is that it is self sufficient. It would carry out the test internally, following a software trigger, without any external input; carry the test; and send out a signature in terms of PASS/FAIL.

Two Pillars of DFT: Controllability & Observability

I haven’t given an equitable share of attention to DFT, and now, it’s time to make some amends!

Just like Timing is built on two pillars: Setup & Hold, entire DFT is built on two pillars: Controllability & Observablity.  

Very often you would find DFT folks cribbing that they can’t control a particular node, or don’t have any mechanism to observe a particular node in question. You may like to review the previous post: DFT Modes: Perspective before proceeding further.

Shifting our attention to the pillars of DFT, let’s define the two.

• Controllability: It is the ability to have a desired value (which would be one out of 0 or 1) at any particular node of the design. If the DFT folks have that ability, they say that that particular node is ‘controllable’. Which in turn means that they can force a value of either 0 or 1, on that node!
• Observability: It is the ability to actually observe the value at a particular node whether it is 0 or 1 by forcing some pre-defined inputs. Note that, unlike the circuit that we make on paper, the SoC is a colossal design and one can observe a node only via the output ports. So, DFT folks actually need a mechanism to excite a node and then fish that value out of the SoC via some output port and then ‘observe’ it!

Ideally, it is desired to have each and every node of the design controllable and observable. But reality continues to ruin the life of DFT folks! (Source: Calvin & Hobbes).

It is not always possible or rather practical to have all the nodes in a design under your control, because of the sheer complexity that modern SoCs possess.

And therefore, it is the reason you would hear them talk about ‘Coverage’. Let’s say coverage is 99%, this means that we have the ability to control and observe 99% of the nodes in the design (A pretty big number, indeed!).

Now let’s take some simple examples.

In the above example, if we have control the flops such that the combo cloud results in 1 at both the inputs of AND gate, we say that the node X is controllable for 1.

Similarly, if we can control any input of AND gate for 0, we say that node X is controllable for 0. Similarly, let’s say we wish to observe the output of FF1. If we can somehow replicate the value of FF1 by making the combo clouds and AND gate transparent to the value at FF1, we say that output of FF1 is observable.

Intuition tells us that for AND gate to be transparent, we should have the controllability of other node for 1. Because when one input of AND gate is 1, whatever is the value at the other input, it is simply passed on!!

Dynamics of Scan Testing

In accordance with the Moore’s Law, the number of transistors on integrated circuits doubles after every two years. While such high packing densities allow more functionality to be incorporated on the same chip, it is, however, becoming an increasingly ponderous task for the foundries across the globe to manufacture defect free silicon.

This predicament has exalted the significance of Design for testability (DFT) in the design cycle over the last two decades. Shipping a defective part to a customer could not only result in loss of goodwill for the design companies, but even worse, might prove out to be catastrophic for the end users, especially if the chip is meant for automotive or medical applications.

Scan testing is a method to detect various manufacturing faults in the silicon. Although many types of manufacturing faults may exist in the silicon, in this post, we would discuss the method to detect faults like- shorts and opens.

Figure 1 shows the structure of a Scan Flip-Flop. A multiplexer is added at the input of the flip-flop with one input of the multiplexer acting as the functional input D, while other being Scan-In (SI).

The selection between D and SI is governed by the Scan Enable (SE) signal.

        Figure 1: Scan Flip-Flop

Using this basic Scan Flip-Flop as the building block, all the flops are connected in form of a chain, which effectively acts as a shift register. The first flop of the scan chain is connected to the scan-in port and the last flop is connected to the scan-out port.

The Figure 2 depicts one such scan chain where clock signal is depicted in red, scan chain in blue and the functional path in black. Scan testing is done in order to detect any manufacturing fault in the combinatorial logic block.

In order to do so, the ATPG tool try to excite each and every node within the combinatorial logic block by applying input vectors at the flops of the scan chain. 

Figure 2: A Typical Scan Chain

Scan operation involves three stages: Scan-in, Scan-capture and Scan-out. Scan-in involves shifting in and loading all the flip-flops with an input vector.

During scan-in, the data flows from the output of one flop to the scan-input of the next flop not unlike a shift register. Once the sequence is loaded, one clock pulse (also called the capture pulse) is allowed to excite the combinatorial logic block and the output is captured at the second flop.

The data is then shifted out and the signature is compared with the expected signature. Modern ATPG tools can use the captured sequence as the next input vector for the next shift-in cycle.

Moreover, in case of any mismatch, they can point the nodes where one can possibly find any manufacturing fault. Figure 3 shows the sequence of events that take place during scan-shifting and scan-capture.

Figure 3: Waveforms for Scan-Shift and Capture

Shift Frequency: A trade-off between Test Cost and Power Dissipation

It must be noted that the number of shift-in and shift-out cycles is equal to the number of flip-flops that are part of the scan chain. For a scan chain with, let’s say, 100 flops, one would require 100 shift-in cycles, 1 capture cycle and 100 shift-out cycles.

The total testing time is therefore mainly dependent on the shift frequency because there is only capture cycle. Tester time is a significant parameter in determining the cost of a semiconductor chip and cost of testing a chip may be as high as 50% of the total cost of the chip.

From timing point of view, higher shift frequency should not be an issue because the shift path essentially comprises of direct connection from the output of the preceding flop to the scan-input of the succeeding flop and therefore setup timing check would always be relaxed.

Despite the fact that higher shift frequency would mean lower tester time and hence lower cost, the shift frequency is typically low (of the order of 10s of MHz). The reason for shifting at slow frequency lies in dynamic power dissipation. 

It must be noted that during shift mode, there is toggling at the output of all flops which are part of the scan chain, and also within the combinatorial logic block, although it is not being captured.

This results in toggling which could perhaps be more than that of the functional mode. Higher shift frequency could lead to two scenarios:

• Voltage Droop: Higher rate of toggling within the chip would result in drawing more current from the voltage supply. And hence there would be a voltage droop because of the IR drop. This IR drop could well drop the voltage below the safe margin and the devices might fail to operate properly.
• Increased Die Temperature: High switching activity might create local hot-spots within the die and thereby increase the temperature above the worst-case temperature for which timing was closed. This could again result in failure of operation, or in the worst case, it might cause thermal damage to the chip.

The post DFT – Design For Testability appeared first on Learn VLSI.

DRV is basically the set of factors based on which the design is characterized. All the standard cell/ macro/ any physical only cell library characterization/ selection is done with DRV kept in mind.

Main DRV are max_transition, max_capacitance, max_fanout. These generally characterize the input speed/slew, output load, driving capacity, routing, congestion and many other factors which affect the quality of the design.

Stages checked: Every stage and have to be solved if exceeding the specified target.

How to fix DRV?

The best approach to fix DRV’s is through implementation tool. One should try to get fixed as many as possible at implementation time only so that there is minimum work to be done manually. However, since, all the modes are not visible at the implementation tool, there are still a few of DRVs left to be fixed manually.

Not only modes, there are DRV violations observed across corners. Since, setup optimization is carried only for WCS corner, the DRV violations of BCS corner are not taken care of by implementation tool.

A general approach to DRV fixing (as we approach tape-out to minimize the disturbance due to cell movement/sizing and/or addition) can include the following steps:

• Make a list of all the DRV violations and find out the unique nets for transition /capacitance violations. Also, prepare a list for unique driver and load for all these nets.
• Run a regression across all your timing modes and corners and find out the setup and hold slack across the unique driver nets.
• We are left with a list of unique nets and their driver/load pins. Try to fix the violations in the below preference order:
  • First, make all the cells to lower Vt’s i.e if HVT, make them SVT or SVT to LVT provided the cells have sufficient hold slack across modes and corners. As we know that ON current through the transistor is proportional to (V-Vt) , hence by lowering the Vt , current increases which will give a better output transition. By swapping the Vt of driver cells, timing /congestion should NOT be impacted much, hence this is the easiest way.
  • Utilize other flavors with same cell footprint/area Some libraries have a number of cells with same area/footprint specifically for the purpose of cell swapping for timing optimization close to tape-out. For instance, one library might have buffers of drive strength 2 and 4 implemented with same area. The library might also have different channel length flavors for same cell with same footprint. We can utilize these so as to take a step forward to DRV closure without any overhead on congestion due to cell movement/sizing. However, here also, we have to be sure that we are not introducing any hold violation due to the cell swap.
  • Increase the Drive strength. Previous steps allow to minimize the number of DRVs without any impact on congestion close to tape-out. However, almost always we are left with a lot of DRVs that cannot be done away with cell swaps without disturbing the design. The first thing, then is to analyze for each of the DRVs is if the DRV can be done away with cell sizing. Since, current is directly proportional to the W/L ratio, hence by increasing the width, it will enhance the output transition and better output load driving capacity. Drive strength should increase in accordance with the violation. Choose proper drive strength of the driving cell so as to compensate the DRV violation. If the magnitude of DRV is small, choose to increase the drive strength by a small factor.
  • Load Splitting (Also called BUS splitting). There are two possible scenarios for this:If the driver has only a single fanout, then the solution is pretty simple. We just have to add a repeater buffer at a strategic location on the net so as to distribute the net load between the driver and newly inserted buffer. The sizes of the current driver and newly inserted buffer have to be decided keeping in mind the load seen by each of these after the new connections will be made.On the other hand, if the driver of DRV net has more than one fanout, then the process is more complex. The solution to the problem requires timing and congestion feedbacks. We should add a buffer strategically after the driver so that the loads are equally distributed between these two cells.
• The most important thing to do after each step is to verify the timing slack and revert the ones resulting in timing degradation. Almost every time, fixing a DRV can result in a hold violation. If it happens, one should revert the fix for the same DRV and add buffers strategically placed so as to distribute the load as discussed later in this text. Doing so, there will be DRV fixed as well as the delay of the buffer will help fixing the hold violation. By repeating the multiple iterations of the above approach we can fix our DRV violations.

Special careabouts/heuristic approach to fix DRVs

If all the DRVs are not fixed, one can try the following steps. First thing to find is the main reason behind the occurring of DRV. There may be many reasons for this, some of the prominent reasons being congestion or timing impact due to fixing the DRV.

• If congestion is the reason, we should try to distribute the less timing critical logic to other regions. One should re-distribute the cells in other regions (with timing iterations) so that the congestion of particular area is gone and one can fix the DRVs in that area.
• If the timing is affected by the Vt swaps / drive strength / buffer insertion, we should back trace the timing path manually and find out a particular node where the slew can be improved and its positive effect is propagated to the culprit cell and improve the input transition of that cell. But one should remember to check the timing slack after every change at any stage.

One of the most important thing to be checked beforehand. One should verify the scaling of tran and cap limit across the timing corners. In some designs, the limits are not scaled properly in a particular PVT corner, hence there are huge no. of violations in that corner. For example – Due to improper scaling of tran and cap limit in best case we saw 10000 drv violations in best corner in comparison to 100 in worst corner.

Slack based Approach: This is the step which we can use in the last stage for the leftover DRV’s. For example, if we have left over DRVs in best case and also hold timing is more critical in this corner than worst.

So, If we can ensure that the hold slack of the timing path is more than the load pin (output load of the DRV net) cell delay, then even if the delay of that cell tends to zero still the hold timing of that path is met.

Hence if this condition is met, we can consider to waive off the DRVs which are not getting fixed.

Approach to fix DRV in PD

• Modify the Driver Cell in different ways.
  • Upsize Cell to higher drive strength
  • Swap Cell to lower channel length
  • Swap Cell to Lower Vt
• Fixing it physically in implementation tool
  • Deploy similar approach (as applied for driver cell) for the logic in driver fan-in cone
  • Load Splitting (Adding Buffers)
  • Try to de-congest the congested area by the movement of spare cells / less timing critical logic

The post Fixing Design Rule Violations (DRV) appeared first on Learn VLSI.

Double patterning is one of several advanced techniques used in the semiconductor industry to continue scaling down device sizes while maintaining performance and manufacturability.

Double patterning is a lithography technique used in VLSI (Very Large Scale Integration) design to overcome limitations in traditional photolithography, particularly as feature sizes shrink in advanced semiconductor manufacturing.

Double patterning lithography is a crucial technique in advanced VLSI manufacturing, particularly as feature sizes continue to shrink beyond the capabilities of traditional lithography methods.

Multiple patterning lithography (MPL) techniques have been used to extend the 193nm lithography to 22nm/14nm nodes.

Possibly further due to the delay of extreme ultra violet lithography and electric beam lithography (EBL) Generally speaking, the MPL consists of double patterning lithography (DPL) and triple patterning lithography (TPL).

There are two main types of DPL with different manufacturing processes:
                  litho-etch-litho-etch (LELE) and
                 self-align double patterning (SADP).

Both of them can be extended for triple patterning. The most important issue for multiple patterning technique is how to successfully decompose the layout into several masks that can be manufactured under current 193nm optical lithography.
 When the pitch between two patterns is less than the lithography threshold, the patterns have to be separated into different masks. This process is called layout decomposition, or coloring.

There are many studies on MPL layout decompositions at the mask synthesis stage to resolve the coloring conflicts, minimize the stitches, balance the mask density, or even mitigate the undesirable overlay effects.

The double-patterning technology (DPT) that means we can continue to use 193nm lithography to produce features at a 64nm pitch in 20nm processes is a breakthrough for manufacturing but an added complication for design.

In double patterning, features that are too close together to be resolved with conventional lithography are separated onto two masks, which are exposed sequentially, with an etch step in between, to form the necessary densely packed features.

Designers must create layouts that can be split (‘decomposed’) into two layers, a process known as coloring, after map-coloring theory.

Achieving such layouts means following new design rules that encapsulate the limitations of the lithographic process and prohibit two polygons of the same color from having particular geometric relationships.

Physical designers have to work with these new rules during placement and routing, considering the costs of decomposability alongside other costs such as timing, power and area.

The physical verification process also has to change, so that it can show that an entire layout can be successfully split onto two masks in a way that meets the foundry’s specifications.
Achieving decomposability

Although foundries will often decompose a layout themselves so that they can optimize the resultant masks for manufacturability, producing decomposable designs means being able to show that applying the foundry rules to a layout can result in successful mask assignments.

Advantages of Double Patterning

Enhanced Resolution: Enables the creation of smaller features beyond the diffraction limit of traditional photolithography.

Increased Circuit Density: Allows for more transistors to be placed on a chip, improving performance and functionality.

Cost Efficiency: Extends the life of existing photolithography tools without requiring the immediate adoption of more expensive extreme ultraviolet (EUV) lithography.

Challenges and Considerations

Design Complexity: Designers must create layouts that can be effectively split into two patterns without violating design rules or creating unprintable features.

Process Variability: Each lithographic step introduces potential variability and defects, requiring robust testing and calibration.

Increased Cycle Time: The additional steps in the manufacturing process can lead to longer production times and increased costs.

Mask Complexity: The creation of masks for double patterning can be more complex and costly due to the need for precise alignment and additional layers.

Double Patterning Workflow

Layer Preparation

• Show a silicon wafer (rectangle) with a photoresist layer (thin rectangle on top).

First Lithographic Exposure

• Illustrate a mask (showing the first pattern) aligned over the photoresist-coated wafer.
• Arrows can indicate exposure to light, highlighting areas that will be developed.

Development of First Pattern

• Depict the wafer after developing, where the photoresist has been removed from the exposed areas, revealing the first pattern.

Etching Process

• Show the wafer being etched, with the first pattern transferred to the underlying silicon.
• Indicate areas that have been etched away.

Second Lithographic Exposure

• Illustrate the application of a second layer of photoresist over the already processed wafer.
• Show a different mask aligned for the second exposure.

Development of Second Pattern

• Similar to the first pattern, illustrate the development of the second pattern.

Final Etching

• Depict the final etched wafer with both patterns clearly defined, highlighting the completed features.

The post DPT in Physical Design appeared first on Learn VLSI.

Yield Classification

Why DFM/DFY ?

Need for DFM/DFY

• Current Lithographic techniques (193nm Laser) cannot print deep-submicron technology patterns without distortion
• Higher design complexity and shrinking device geometries
• More devices per unit area on a chip (device density)

Importance of DFM/DFY

• Impact of variations, if not addressed in the design, will cause manufacturing issues, such as poor yields, long yield ramp-up times and poor reliability
• The chips may completely miss the market window or may hit the market window but not economically viable
• The chips may still function, but not at the required/expected speed
• The chips appear to be reliable after volume production, but may suffer catastrophic failures in the field earlier than their expected life-cycle

DFM/DFY Solutions

DFM: Recommendations

Wire Spreading

• The wire distribution spreads wires that are on the same metal layer as well as across different metal layers
• The benefits gained from lower routing density are in improved manufacturing yield, reduced crosstalk noise, crosstalk delay and random particle defects

Metal Fill

• Dummy metal fill
• Timing aware metal fill
• Unbalanced metal density across a chip may cause yield loss, so fill the empty spaces in the design with metal wires to meet the metal density rules required by most fabrication processes
• Improved surface planarity helps decrease manufacturing variations that contribute to timing variability

Hot Spots and Critical Area Analysis (CAA)

• Hot Spot/ Critical Area is the region at the center of a random defect which will cause circuit failure (yield loss)
• By analyzing the critical areas, defect-limited yield can be estimated based on the probability of the failures of vias and point defects on routing
• The larger the defect size, the larger the Critical Area

• Chemical-Mechanical Polishing (CMP) is a technique for surface smoothing and material removal process to get globally planar wafer surface
• Simultaneous polishing of copper, dielectric and barrier
• Combination of chemical and mechanical interactions
  • The chemical effect by pH regulators, oxidizers or stabilizers
  • The mechanical action by submicron sized abrasive particles contained in the slurry flow between the polishing pad and the wafer surface
• Dishing
  • Difference between the height of the copper in the trench and the height of the dielectric surrounding the copper trench
  • Copper dishing is higher for wider copper line or the spacing
  • It can thin the wire or pad, causing higher-resistance wires or lower reliability bond pads
• Erosion
  • Difference between the dielectric thickness before CMP and after CMP
  • Dielectric erosion is higher for higher density
  • Erosion can result in a sub-planar dip on the wafer surface, causing short-circuits between adjacent wires on next layer
• On-Chip Variation (OCV) from the interconnect thickness variation due to CMP becomes relatively larger and needs to be taken into consideration in the postlayout RC extraction and timing flow
• Solution to CMP is CMP hotspot detection and fixing

CMP aware-design

• Various degrees of Copper Dishing and Dielectric Erosion occur at different densities and metal line widths
• In advanced nodes minimal material removal with atomically flat and clean surface finish has to be achieved
• CMP is influenced by line width and pattern density
• The dishing and erosion increase slowly as a function of increasing density and go into saturation when the density is more than 0.7
• Oxide erosion and copper dishing can be controlled by area filling and metal slotting

Redundant Via

• Redundant Vias use two, or more, Vias to connect the upper and lower routing layers together
• Replacing single Vias with redundant (or double) Vias on signal nets improves reliability and reduce yield loss, due to via failures
• Critical Area Analysis (CAA) identifies the requirement of Redundant Vias

Resolution Enhancement Techniques (RET)

• RET are methods used to modify photo-masks to compensate for limitations in the lithographic processes used to manufacture the chips
• Have significantly increased the cost and complexity of sub-micron nanometer photomasks
• The photomask layout is no longer an exact replica of the design layout
• As a result, reliably verifying RET synthesis accuracy, structural integrity, and conformance to mask fabrication rules are crucial for the manufacture of nanometer regime VLSI designs

Litho Process Check (LPC)

• Problem: Some DRC clean layouts do not print on silicon
• Solution: Must-have litho hotspot detection and fixing of design

Layout Dependent Effects

• Well Proximity Effect (WPE)
• Poly Spacing Effect (PSE)
• Length of Diffusion (LOD)
• OD to OD Spacing Effect (OSE)
• Layout Patterning Check (LPC )
• OD/Poly Density

Resolution Enhancement Techniques

Types of RET

• Optical Proximity Correction (OPC)
• Scattering Bars (SB)
• Double Patterning (DP) or Multiple Patterning
• Phase Shift Masking (PSM)
• Off-axis Illumination (OAI)

Optical Proximity Correction (OPC)

• OPC is a Photo-lithography Enhancement technique commonly used to compensate the mask pattern for image errors due to diffraction or process effects (by reducing the value of the k1 factor in CD equation)
• OPC is an effective way to deal with geometry distortion from design to chip; however, it does come at a price
• First, there is the cost of the EDA tools you need to implement the OPC corrections
• Second, you have an exponential increase in volume of the data representing the chip’s layout, along with a huge increase in the time it takes to process this data and prepare it for photo-mask generation

Multiple Patterning

• Involves decomposing the design across multiple masks to allow the printing of tighter pitches
• 38-nm features with 193-nm light water immersion lithography is the limitation with the current lithographic process
• Multiple Patterning is a technique used in the lithographic process that can create the features less than 38nm at advanced process nodes
• Multiple patterning basically changing the value of K1 in the Critical Dimension equation
• Double Patterning
  • Double patterning counters the effects of diffraction in optical lithography
  • Diffraction effects makes it difficult to produce accurately defined deep sub-micron patterns using existing lighting sources and conventional masks
  • Diffraction effects makes sharp corners and edges become blur, and some small features on the mask won’t appear on the wafer at all
  • Double patterning is expensive because it uses two masks to define a layer that was defined with one at previous process nodes

Phase Shift Masking (PSM) (not considered in PD)

• Phase-shift masks are photo-masks that take advantage of the interference generated by phase differences to improve image resolution in photolithography
• Controlling the phase enables constructive or destructive interference at desired locations in the image plane, thus sharpening or dulling the contrast as desired
• These are photo-masks with structures that manipulate not only the amplitude of the transmitted waves but also their phase
• Etching quartz from certain areas of the mask (alt-PSM) or replacing Chrome with phase shifting Molybdenum Silicide layer (attenuated embedded PSM) to improve CD control and increase resolution
• There exist alternating and attenuated phase shift masks
• Types of masks
  • Conventional (binary) mask, Alternating phase-shift mask, Attenuated phase-shift mask

Off-Axis Illumination (OAI) (not considered in PD)

• Off-axis illumination is one of the practical techniques to enhance resolution of a given optical system with bigger advantage of improvements in depth of focus
• The specific illumination geometry is designed to enhance the contrast in the wafer plane of the photo-mask features whose dimensions are most Critical
• With OAI, resolution of a given system can be improved without going for shorter wavelength or higher numerical aperture (NA)
• This technique basically has no on-axis illumination component as oppose to partial coherence
• The shape and size of the source plays an important role when different conditions of mask features such as density and orientation are considered
• To obtain the highest resolution, illumination of the photo-mask is not performed by a discshaped source
• The angular distribution of the illumination beam may have a complex structure, such as an annulus, a set of off-axis circles, or even a continuously varying profile

The post Design for Manufacturability (DFM) appeared first on Learn VLSI.

What is Max transition time in VLSI?

Maximum transition time: The transition time of a net is the longest time required for its driving pin to change logic values.

Transition time is decided on the basis of rise time and fall time. This constraint (max_transition) is based on the library data. For the nonlinear delay model (NLDM), output transition time is a function of input transition and output load.

How to calculate Max transition?

CMOS delay model: Transition Time = Drive R X Load C Non­linear delay model: Transition Time from table lookup and interpolation/extrapolation.

You can make the transition time of each net less than the “max_transition” value (defined in the library file) by adding a buffer at the output of driving gate.

If your design uses multiple technology libraries and each has a different default_max_transition value, synthesis tools uses the smallest max_transition value globally across the design.
This info is present in the .lib file (liberty file).

What’s the significance of max_transition in the design? 

 Lot of people has different views for this. Like if you will increase the max_transition value then your delay will increase, so library has to characterize for those delay value also and so on. 

 Case 1:

 Power consumption is becoming a major issue. Everyone wants to reduce the power consumption. Powers are of 2 type­ Switching and Leakage power.

 Consider the  inverter shown below consisting of a PMOS  to VCC and  NMOS to GND.

when  input is low the PMOS is  transistor is ON and the n­channel is OFF. It will cause current to flow from VCC and  output is  high state.
When input is high PMOS is OFF and NMOS is ON. It will cause current flows to GND, output is low.

In both cases there is no current flows from VCC to GND directly However, when switching from one state to another, the input crosses the threshold region, causing the n­channel and the p­channel to turn on simultaneously, generating a current path between VCC and GND.

This current surge can be damaging, depending on the length of time that the input is in the threshold region (Low Level threshold to High Level threshold).

Now, if the transition time is large means length of time to change the logic is large. So both the channel turns on simultaneously more time. Means more Switching power consumption.

So library characterization team has to come up with a maximum value of transition time either specific to all cells in a particular library or individual cell.

 Case 2:  Frequency dependency

we know that that cell delay is a function of input trans and output load. when input trans is too much cell delay will be increased depends on the library characterization. 

1. when Design is working on high freq (1GHz) and  if there are more number of levels in that path and max_trans limit is too much from the library then we will get the cell delay more, it will cause higher delay for the cell.  

2. when freq is less then even though max_trans limit is more we will not see timing violation because of the cell delay.

It can vary with the operating frequency of a cell. Since this parameter is based on rise/fall time and rise/fall time is the time required to charge/discharge input capacitance load of the pin.

Now if operating frequency vary, the capacitive load vary as per relationship of Xc=1/ωC . If multiple clocks launch the same paths, the most restrictive value is used.  

Now what I am trying to say that max_trans also depends on the freq to meet the tiiming.  we need to set the max_trans limit or interpolate that value so that we will get minimum  cell delay.

Cause of failure of trans 

(1) input port transition;

(2) input clock transition; (important)

(3) wire length…

(4) Fanout…

(5) Gate drive strength…

The transition is decided by two factors: one is the input slew (transition), one is output load(including wire cap and fanout).

If anyone of them is over the limit of Lookup Table in std cell library, inaccuracy is produced. So, fixing max_transition violation is inevitable.

If input slew is too slow, increment the driver strength.

If output load is too high, add some buffer.

Now, you need look into these two factors.

Debug if there are any design consistency isses

Use the check_design command to verify the design consistency. The check_design command reports a list of warning and error messages,

By default, the check_design command reports all warning messages. You can reduce the output by summarizing the warnings (by using the -summary option) or by disabling the warnings (by using the -no_warnings option).

you can also use the following method to fix max trans

1. Increase the drive capacity of the book to increase the voltage swing or decrease the capacitance and resistance by moving the source gate closer to sink gate.
2. Increase the width of the route at the violation instance pin. This will decrease the resistance of the route and fix the transition violation

The post Max Transition Violation appeared first on Learn VLSI.

What is DRC?

DRC stands for Design Rule Check

DRC:

It is actually used for making sure layout of a design must be in accordance with a set of predefined technology rules given by the foundry for manufacturability.

Stage checked at: Every stage after placement. Mainly the number should be low post route stage.

The main DRCs include shorts, opens, spacing between metals, n and p wells, same and different nets, min length, area and enclosure etc.

• Design Rule Check (DRC) is the process of checking physical layout data against fabrication-specific rules specified by the foundry to ensure successful fabrication.
• Process specific design rules must be followed when drawing layouts to avoid any manufacturing defects during the fabrication of an IC.
• Process design rules are the minimum allowable drawing dimensions which affects the X and Y dimensions of layout and not the depth/vertical dimensions.
• As Technology Shrinks
  • Number of Design Rules are increasingComplexity of Routing Rules is increasingIncreasing the number of objects involved
• • More Design Rules depending on Width, Halo, Parallel Length
• Violating a design rule might result in a non-functional circuit or low Yield.

Design Rule examples

• Maximum Rules: Manufacturing of large continuous regions can lead to stress cracks. So ‘wide metal’ must be ‘slotted’ (holes)
• Angles: Usually only multiples of 45 degree are allowed
• Grid: All corner points must lie on a minimal grid, otherwise an “off griderror” is produced
• Minimum Spacing: The minimum spacing between objects on a single layer
• Minimum Width: The min width rule specifies the minimum width of individual shapes on a single layer
• Minimum Enclosure/ Overlap: Implies that the second layer is fully enclosed by the first one
• Notch: The rule specifies the minimum spacing rule for objects on the same net, including defining the minimum notch on a single-layer, merged object
• Minimum Cut: the minimum number of cuts a via must have when it is on a wide wire

DRC have 2 categories – Base Layer DRC’s and Metal DRC’s

Base Layer DRC’s:

• Base layer means all layers upto contact/metal 1. In Base layer, DRC flow rules will be checked:
  • Base DRC’s are spacing rules for geometries inside transistor (Well spacing, Poly spacing, Poly width)
  • Tap cell requirement
  • Well continuity (after routing fill empty space using spare cells)
• Fixes:
  • Make sure design is placed legallyNo cell overlaps & no gaps
  Most of the times, base DRC’s will be clean if we ensure above two conditions.

Some of the Causes for Base Violations are:

1. Missing Endcap/WellTap/Decaps/Filler cells
2. Incorrect filler placement
3. Incorrect filler addition
4. Overlap issue or issue in the Internal Structure of the particular memory down model (Hard Macro/IP)
5. Memory not on grid
6. Orientation issue
7. Input gate integrity problem
8. Legalization issue
9. Abutment requirement between two Memories is not met (Memory Spacing Rule varies in accordance to technology and foundry)

Metal DRC’s:
Metal DRC means from contact to all the routing layers. Basic metal DRC’s are:

• Width (min & max)
• Spacing (min)
• Via enclosure (size of min cut, min via to via spacing in multi cut Vias)

 In some cases, the via enclosure is quite large compared to metal width due to large via enclosure. Thee other long net passing each other and dropped in via will create a different spacing violation.

Solution:

To fix this type of spacing violation, the net needs to be placed away from the via, or different size vias need to be inserted so it will meet the same net spacing requirement. In above case, routing taken in reverse U shape will meet the spacing requirements as below.

  All foundries have their own design rules for masking. They have consistent process to convert GDS II in to real layout/final product. As per technology and process information they define some set of rules which has to follow by Physical Design Engineer while delivered GDS II.

·   Design Rules defines shapes/size/spacing and many other complex rules of each metal layers. It starts from your substrate to Newell to top metal layers.

·   All rules are define in one rule deck file, Its nothing but your drc runset file. For routing purpose, minimum set of rules will be define your technology file.  Which extension is .tf.

·  Each foundry have its own manufacturing design rules. DRC rules becoming complex as we are going sub-micron technology.

· DRC doesn’t ensure that your device will work properly, It ensure it will get manufactured properly.

· Once Design is DRC clean, then only correct parasitic extraction we can get.

DRC Flow

 DRC clean up comes in Physical Verification steps (After routing). If you are working on below 90nm , Metal Fill is required. So once you finish metal fill you will have corrected DRCs errors. Below DRC flow input/output and some basic examples are given. 

INPUT

·         GDS II of your block/section/chip in format of .stm or .oasis

·         DRC runset file. Extenuation of runset file depend on which EDA tools you are working on. Normally it’s in .ev or .rs

OUTPUT

•  Marker based error file.
• If you are using Synopsys Tools ( IC Validator ) It generates .vue file.
• This files can be loaded and we can go to one by one markers and clean drcs.

Basic Examples.

1.       DRC_M2: Minimum distance BW M2 should be  0.070.

Error Description: Here spacing BW metal2 is 0.046 which should be 0.070.    

Solution: Stretch metal/fill by keeping spacing 0.070 BW them.

2. DRC_M4 : Width1 to width2 spacing should be 0.040

Error Description: Here two different width of metal4 width to width spacing is not as per rule

The post Design Rule check in PV appeared first on Learn VLSI.

Pre-Placement Optimization

Pre-Placement Optimization Goals

• Routability
• Performance (Timing)
• Power (with Cells)

Optimizations before Placement

• Delay models must be removed (if any)
• Zero-RC (0-RC) Optimization
• Isolation Cell Insertion
• Multi Corner Multi Mode (MCMM) settings before Std. Cell Placement

Zero-RC Optimization

• Optimizes the netlist without any delay models, thus provides an optimal starting point for placement
• Timing during 0-RC Opt and that of during Synthesis has to be matched
• Else indicate problems in the Technology File, Timing Library, Constraint Files, or overall design
• Logical restructuring and up/down size are optimizations at the 0-RC stage

Note: Take care of don’t use cells while doing optimization

Placement

• Placement is the process of placing standard cell in the design. the tool determines the location of each standard cell on the die. the tool places these based on the algorithms which it uses internally.
  
• Placement does not just place the standard cells available in the synthesized netlist. it also optimizes the design. placement also determines the routability of design.
  
• Placement will be driven by different criteria like timing driven, congestion driven and power optimization.

Placement Objectives

• Total wire length
• Routability
• Performance
• Power
• Heat distribution

Timing checks only with slow corners at Placement stage

Only Setup Time check, since buffers are getting added during Clock Tree Synthesis

Goals of Placement:

• Timing, Power and Area optimizations
• Minimum congestion
• Minimal cell density, pin density and congestion hot-spots
• Minimal timing DRVs

Inputs of Placement:

• Technology file (.tf)
• Netlist
• SDC
• Library files (.lib & .lef) & TLU+ file
• Floorplan & Powerplan DEF file

Things to be checked before placement

1. Check for any missing/extra placement & routing blockages.
2. Don’t use cell list and whether it is properly applied in the tool.
3. Don’t touch on cells and nets (make sure that, these are applied).
4. Better to have limit the local density (otherwise local congestion can create issue in routing/eco stage).
5. Understand all optimization options and placement switches set in the tool.
6. There should not be any high WNS timing violations.
7. Make sure that clock is ideal network.
8. Take care of integration guidelines of any special IPs (these won’t be reported in any of the checks). Have custom scripts to check these guidelines.
9. Fix all the hard macros and pre-placed cells.
10. Check the pin access

• Before the start of placement optimization all wire load model (WLM) are removed.
• Placement uses RC values from virtual route (VR) to calculate timing.
• VR is the shortest manhattan distance between two pins.
• VR RCs is more accurate than WLM RCs.

Placement Methods

Timing Driven Placement

• To Refine placement based on congestion, timing and power
• To optimize large sets of path delays
• Net Based

Congestion Driven Placement

• To distance standard cell instances from each other such that more routing tracks are created between them

– Control the delay on signal path by imposing an upper bound delay or weight to net

Global/ Coarse Placement

• To get the approximate initial location
• Cells are not legally placed and there can be overlapping

Detail/ Legal Placement

• To avoid cell overlapping
• Cells have legalized locations
• Legalize placement will place the cells in their legal position with no overlap

Placement Legalization

• Placed Macros are legally oriented with Standard Cell Rows

In-Place Optimizations

• Scan Chain Reordering: DFT tool flow makes a list of all the scan-able flops in the design, and sorts them based on their hierarchy. In APR tool scan chains are reordered on the basis of placement of flops & Q-SI routing. This is nothing but scan-chain reordering. Scan-chain reordering helps to reduce congestion, total wire-length etc…

• After Placement, report Congestion, Utilization and Timing
• Tie off cell instances provide connectivity between the Tiehigh and Tie-low logical inputs pins of the Netlist instances to Power and Ground
• Tie off cells are placed after the placement of Standard Cells
• After placement check the Cell Density

Global Route (GR)

• Whole region is divided into an array of rectangular sub-regions each of which may accommodate tens of routing tracks in each dimension called Global Cells
• Global Route is performed to estimate the inter-connect parasitics and Routing Congestion Map

Placement Opt./ Pre CTS Optimization

Cell Sizing

• Sized up/ down to meet optimizing for timing and area
• Up sizing will give timing advantage and Down sizing will give area advantage

VT Swapping

• To optimize for leakage power (HVT, RVT/SVT, LVT)

Cloning

• To reduce fanout

Buffering

• Long nets are buffered or remove buffers to bring the timing advantage

Re-Buffering

• To improve slews, reduce net capacitance and reduce fanout

Logical Restructuring

• To optimize timing and area without changing the functionality of the design
• Breaking complex cells into simpler cells or vice versa

Placement Qualifications

• Unplaced cells (should be 0)
• Cells overlap (should be 0)
• Utilization
• Minimal timing issue
• Minimal congestion issue
• Minimal timing DRVs
• Total area after optimization

Placement Output

• Congestion report
• Timing report
• Design with all std cells placed in core area
• Logs
• Placement DEF file

The post Placement in VLSI Physical Domain appeared first on Learn VLSI.

fig(i) Process Antenna Effect

• If the area of the layer connected to the gate directly or connected to the gate through the lower layers is large compared to the area of the gate, then the static charges accumulated on that particular layer during plasma etching may get discharge through the gate resulting into damage of the oxide layer and permanent damaging of the transistor.

Antenna Ratio Checks

Antenna rules are defined in LEFs. These rules are different for metal layers and vias. Generally, either of the two checks are performed from the following,

• Cumulative Area Ratio Check (CAR): This check will take into the account the effects of the current layer in check along with the layer(s) that are beneath it i.e. from M1 layer up to the layer that is being checked.
• So, when calculating Antenna Ratio (metal area/gate area); metal area will be summation of the area of the current layer in check plus the area of the layer(s) beneath it; though most of the LEFs won’t combine metal area and cut area and hence most of the tool will not include via area when calculating antenna ratio on metal layer.
• Most of the LEFs are defined with the rules supported for this check. If the rules related to ANTENNA check in LEF is associated with keyword CUM (cumulative); than the LEF is defined with the CAR check.
• The tool will compare Cumulative Area Ratio (CAR) of metal layer with ANTENNACUMAREARATIO for the layer in check in LEF; and if the CAR exceeds this value, then a violation occurs.
• If a diode is attached with the gate, then CAR of metal layer will be compared to ANTENNACUMDIFFAREARATIO-this value will be larger than the ANTENNACUMAREARATIO as connecting a diffusion region(diode) to the gate will relax the antenna ratio.
• Alternatively, instead of specifying a single limit for antenna ratio, some LEFs specify a piece-wise linear (PWL) model of diffusion area and antenna ratio limit.
• Partial Area Ratio Check (PAR): This check considers only the current layer (single layer) area while calculating the antenna ratio. It neither consider the layers beneath the current layer nor the via area. When the number of total routing layers in a technology are less, this check is sufficient for calculating process antenna ratio.

Process Antenna Fixes

• Routing on Higher Metal Layer: A part of long interconnect can be taken to higher metal routing layer and back. This in known as metal jumping.
• This metal jumping is usually done near to the load. This metal jumping will break the long interconnect and hence the charge collected on the long interconnect will not discharge through gate oxide because the higher metal layer is not yet fabricated. This solution may increase the routing congestion on higher metal layers.
• Adding Dummy Load: Antenna Rule is the ratio of metal area to gate area. So increasing gate area will reduce the antenna ratio. Gate area can be increased by adding a dummy load (mostly inverter or buffer) and connecting the gate of dummy cell to the gate of the cell with high antenna ratio. Output of dummy cell is kept floating.
• Reduce the via-area: Large via area also results in process antenna violation. Converting multi-cut vias to double-cut via or double-cut vias to single-cut via reduces the cut area. Though it may impose serious reliability issues such as electromigration.
•  Diode Insertion: Connecting a diode (diffusion) to the gate electrode (load) provides a discharging path for the static charge present on the metal layer (antenna) as shown in fig (ii). Diode should always be connected in reverse bias, with cathode (diffusion) connected to gate electrode and anode (substrate) connected to ground potential.
• Generally, avalanche diode is preferred due to its capability of withstanding high voltage in reverse bias. So, when plasma etching induces negative charges, avalanche diode works in forward bias shunting all the current to ground and when plasma induce positive charges, diode works in reverse-bias mode and avalanche breakdown occurs due to high voltage across it and hence allowing high current to pass through it.
• Generally, other diodes (pn diode, Zener diode etc) suffers a permanent failure once breakdown occurs but avalanche diodes are designed (less doping concentration) to break down at a high reverse voltage without getting damaged.
• Insertion of diode doesn’t affect the normal operation as normal operation works at very low voltage that is not capable of causing an avalanche breakdown.

fig(ii) Diode Insertion

• Automatic Fixes: Clock pins are highly susceptible to antenna violation as most of layers in clock net are wide(NDR) and vias are also large in terms of area(multi-cut/NDR-via).
• So, most of the PnR tool inserts diode automatically on the pins with high antenna ratio. Though inserting diodes has it own demerits.
• Firstly, adding high number of diodes will occupy more space that are reserved for standard cells to place; they dissipate heat (leakage power) and lastly, they increase the diffusion capacitance seen by driver pin which will impact the performance.
• Alternatively, most of the routing engine can be instructed to go for metal hopping/jumping to solve antenna violation and avoid diode insertion.

The post Process Antenna Rule appeared first on Learn VLSI.

• Excessive current density within interconnects – which if not effectively mitigated causes electromigration (EM) .
• Electromigration (EM) is the gradual displacement of metal atoms in a semiconductor. It occurs when the current density through the conductor is high enough to cause the drift of metal ions .

Failure Mechanism

1. Non-uniformity in lattice structure of Interconnects: There exists a non-uniformity of metal interconect structures during fabrication which may results in either void or hillocks.

This non-uniformity is more dominant at vias/contacts as there is a sudden change in conductor area through which current is flowing and ultimately it affects the current density (J= I/A). If the current density is too high, it results void that cause breaking of line or hillocks that causes short-circuits to adjacent lines.

2. Thermal Accelerating Effects: Once the void is formed on a line, the current density increases as the area of conductor tends to reduce.

This hampers the uniform temperature that was established along the interconnect and increases the local temperature which further accelerates the void growth ultimately breaking the line.

This increase in temperature due to current density is termed as Joule Heating which is directly proportional to the square of the current density. This further widens the void ultimately breaking the line.

3. The Self-Heating Effect: Self heating refers to the the heat generated by current carrying element. Moreover the heat dissipation mechanism of Silicon On Insulator -FINFETs is poor as the only way to dissipate heat is through gate because oxide layer beneath the channel is a poor conductor of heat compared to silicon that is used in bulk-FINFETs.

So, in addition to the wire self-heating, FINFETs also contributes in the heat transfer to this signal nets which increases the local temperature making wire more prone to electromigration.

Important Terms related to signal-EM

1. Irms/Ilimit ratio: When we are analysing AC signal-em on signal nets and on clock nets; we are generally interested in rms current check rather than peak and average current because the principle concern is overheating of wire that causes voids and/or hillocks that grows with time and it’s not an one-time event.

Current limit (Ilimit) is specified by foundaries and it is mentioned in LEFs for each metal layer and via. A piece-wise linear model of metal layer width (cut-area in case of vias) and effective frequency is specified to calculate current limit (Ilimit).

The calculated rms current (Irms) should be within this limit to avoid electromigration.

2.Effective Frequency: Electromigration also depends on slew rate; faster the transition, the more signal net will be prone to EM violation. Hence it is necessary to know how fast the signal/clock net is changing.

Effective frequency represents the toggle rate of signal nets with respect to clock signal. By default, the toggle rate on signal nets will be 100% which means data on signal line will toggle once at every clock cycle.

Hence by default, the effective frequency on signal nets would be half of the input clock frequency as data only changes at half rate of input clock.

Similarly, the toggle factor for clock nets will be 200%. Alternatively, we can specify signal net frequency (toggle rate) using VCD/TCF/SAIF file also.

3. DeltaTemp: Another important factor affecting electromigration is temperature rise. This value specifies the allowed temperature rise along the net.

This temperature rise is due to the current (Irms) flowing through the net which will causes power(heat) dissipation (P = I²R). DeltaT limit is calculated from Irms limit specified in LEF. It’s unit is specified in °C.

Causes of Signal EM

1. High Fanout Net: When multiple fanout switches together, a high current is drawn from the driver. This high current generates considerable heat that may displace the metal atoms resulting in either voids or hillocks.

2. Driver size: A cell size of x16 and x12 unnecessarily induces a large current in the interconnects which heats up the wire. This large drivers causes a high Irms value and a high DeltaT value.

Moreover, FINFETs due to its 3D structure has high channel volume that conducts more current for the same driver size compared to planar transistor.

3. Fast Transition: Fast transition of data is the requirement in high speed chips but it has some of its own reliability problems. Faster transition means high velocity electrons which when collides with the atoms of interconnect causes them to break from the lattice structure and causing voids and hillocks.

Clock nets have the highest probability of suffering from this issue as it has high frequency signal passing through it, with very high fanout and moreover they are global nets (long nets) that spans across the chip.

4. Long Net: Sometimes, EM may arise with a single fanout also. The reason being long resistive interconnect. As the length of the interconnect increases, it’s resistance increases (R=ρl/A).

This high resistance causes a high localized temperature along the net which further increases the resistance resulting metal reliability problems and increase in Delta Temp value.

Signal EM Fixes

Manual Fixes:

1. Driver Downsizing: Downsizng the driver cell will reduce the current density in the interconnects and reduces the risk of EM failure.

Though we have to make sure that downsizing the driver is not affecting the timing or transition time in that path. We can check the timing of the EM affected path before & after down-sizing the driver using STA tools like prime time, tempus.

2. Non-Default Rule (NDR) on the victim nets: Applying NDR will increase the metal width which will in-turn increase it’s current carrying capability.

Safest way is to apply NDR on the whole net but if the design is too congested, then applying NDR on the whole net may result in high number of shorts or detouring of that net which will affect timing. Alternatively, we can apply NDR on only those segments (layers) of the net which have high Irms.

3. Insert Buffer: Inserting a buffer or a pair-of-inverters will break the long nets and reduces the resistance. We have to make sure that the EM affected path has enough timing margin so that adding a buffer won’t degrade the timing.

We can check that in STA tool but adding a buffer will add a new net whose extraction value will be absent and STA tools will not show the correct delay(it will only include cell delay but net delay will be zero) of that path after adding a buffer.

4. Routing on Higher Layers: Higher routing layers are less resistive and have higher current carrying capabilities making nets less prone to electromigration.

Though we have to make sure that before routing on higher layer, the routing congestion of those higher layers should be less or else it will result in shorts and detouring.

5. Use multi-cut Via or NDR via: Electromigration is more dominant on vias as there is sudden change in area through which current is flowing. Usage of multi-cut via will increase the via area, reduces the resistance and also increases the reliability of the wire. NDR-via are larger in size with larger contact area.

6. Break the Fanout: High fanout causes a high current to be drawn from the driver. This can be avoided by splitting the fanout using buffers. Generally, the buffer we add should be of same size or one size lower than the driver so that timing is not much affected. Though this is not a strict rule.

Automatic Fixes:

1. NDR aware PnR: During global routing at placement, placement engine will occupy more tracks for the nets wherever possible so that the net can be applied with NDR at routing stage. This method is very effective if design is less congested.

2. Hold Fixing: Enabling hold fixing during PnR or fixing hold timing prior to EM fixing at sign-off considerably reduces the EM violating nets as hold fixing will add buffers that will ultimately break the nets.

Morover, in most of the PnR tools, adding buffer will be timing-aware in a sense that it will make sure that the setup time will not get deteriorate.

3. Making high-driving cells as Don’t Use: If EM violation is high in number, we can run an experiment with setting high driving cell (x16 and x12) as don’t use.

Setting them as don’t use will avoid the usage of those cells throughout the PnR flow. Though doing so, it may affect the transition time and performance.

The post Electromigration Causes and Fixes appeared first on Learn VLSI.