Design Rule check in PV

Physical Design Verification

What is DRC?

DRC stands for Design Rule Check

DRC:

It is actually used for making sure layout of a design must be in accordance with a set of predefined technology rules given by the foundry for manufacturability.

Stage checked at: Every stage after placement. Mainly the number should be low post route stage.

The main DRCs include shorts, opens, spacing between metals, n and p wells, same and different nets, min length, area and enclosure etc.

• Design Rule Check (DRC) is the process of checking physical layout data against fabrication-specific rules specified by the foundry to ensure successful fabrication.
• Process specific design rules must be followed when drawing layouts to avoid any manufacturing defects during the fabrication of an IC.
• Process design rules are the minimum allowable drawing dimensions which affects the X and Y dimensions of layout and not the depth/vertical dimensions.
• As Technology Shrinks
  • Number of Design Rules are increasingComplexity of Routing Rules is increasingIncreasing the number of objects involved
• • More Design Rules depending on Width, Halo, Parallel Length
• Violating a design rule might result in a non-functional circuit or low Yield.

Design Rule examples

• Maximum Rules: Manufacturing of large continuous regions can lead to stress cracks. So ‘wide metal’ must be ‘slotted’ (holes)
• Angles: Usually only multiples of 45 degree are allowed
• Grid: All corner points must lie on a minimal grid, otherwise an “off griderror” is produced
• Minimum Spacing: The minimum spacing between objects on a single layer
• Minimum Width: The min width rule specifies the minimum width of individual shapes on a single layer
• Minimum Enclosure/ Overlap: Implies that the second layer is fully enclosed by the first one
• Notch: The rule specifies the minimum spacing rule for objects on the same net, including defining the minimum notch on a single-layer, merged object
• Minimum Cut: the minimum number of cuts a via must have when it is on a wide wire

DRC have 2 categories – Base Layer DRC’s and Metal DRC’s

Base Layer DRC’s:

• Base layer means all layers upto contact/metal 1. In Base layer, DRC flow rules will be checked:
  • Base DRC’s are spacing rules for geometries inside transistor (Well spacing, Poly spacing, Poly width)
  • Tap cell requirement
  • Well continuity (after routing fill empty space using spare cells)
• Fixes:
  • Make sure design is placed legallyNo cell overlaps & no gaps
  Most of the times, base DRC’s will be clean if we ensure above two conditions.

Some of the Causes for Base Violations are:

1. Missing Endcap/WellTap/Decaps/Filler cells
2. Incorrect filler placement
3. Incorrect filler addition
4. Overlap issue or issue in the Internal Structure of the particular memory down model (Hard Macro/IP)
5. Memory not on grid
6. Orientation issue
7. Input gate integrity problem
8. Legalization issue
9. Abutment requirement between two Memories is not met (Memory Spacing Rule varies in accordance to technology and foundry)

Metal DRC’s:
Metal DRC means from contact to all the routing layers. Basic metal DRC’s are:

• Width (min & max)
• Spacing (min)
• Via enclosure (size of min cut, min via to via spacing in multi cut Vias)

 In some cases, the via enclosure is quite large compared to metal width due to large via enclosure. Thee other long net passing each other and dropped in via will create a different spacing violation.

Solution:

To fix this type of spacing violation, the net needs to be placed away from the via, or different size vias need to be inserted so it will meet the same net spacing requirement. In above case, routing taken in reverse U shape will meet the spacing requirements as below.

  All foundries have their own design rules for masking. They have consistent process to convert GDS II in to real layout/final product. As per technology and process information they define some set of rules which has to follow by Physical Design Engineer while delivered GDS II.

·   Design Rules defines shapes/size/spacing and many other complex rules of each metal layers. It starts from your substrate to Newell to top metal layers.

·   All rules are define in one rule deck file, Its nothing but your drc runset file. For routing purpose, minimum set of rules will be define your technology file.  Which extension is .tf.

·  Each foundry have its own manufacturing design rules. DRC rules becoming complex as we are going sub-micron technology.

· DRC doesn’t ensure that your device will work properly, It ensure it will get manufactured properly.

· Once Design is DRC clean, then only correct parasitic extraction we can get.

DRC Flow

 DRC clean up comes in Physical Verification steps (After routing). If you are working on below 90nm , Metal Fill is required. So once you finish metal fill you will have corrected DRCs errors. Below DRC flow input/output and some basic examples are given. 

INPUT

·         GDS II of your block/section/chip in format of .stm or .oasis

·         DRC runset file. Extenuation of runset file depend on which EDA tools you are working on. Normally it’s in .ev or .rs

OUTPUT

•  Marker based error file.
• If you are using Synopsys Tools ( IC Validator ) It generates .vue file.
• This files can be loaded and we can go to one by one markers and clean drcs.

Basic Examples.

1.       DRC_M2: Minimum distance BW M2 should be  0.070.

Error Description: Here spacing BW metal2 is 0.046 which should be 0.070.    

Solution: Stretch metal/fill by keeping spacing 0.070 BW them.

2. DRC_M4 : Width1 to width2 spacing should be 0.040

Error Description: Here two different width of metal4 width to width spacing is not as per rule