What is Floorplanning?
A floorplanning is the process of placing blocks/macros in the chip/core area,thereby determining the routing areas between them.
Floorplan determines the size of die and creates wire tracks for placement of standard cells. It creates power ground(PG) connections.
It also determines the I/O pin/pad placement information.
Before starting with the floorplan we will perform import design, sanity checks and partitioning.
Sanity checks in Floorplanning
Sanity Checks mainly checks the quality of netlist in terms of timing.
— It also consists of checking the issues related to Library files, Timing Constraints, IOs and Optimization Directives
1. Library checks
• Missing cell information
• Missing pin information
• Duplicate cells
2. Design checks
• Inputs with floating pins
• Nets with tri-state drivers
• Nets with multiple drivers
• Combinational loops
• Empty modules
• Assign statements
3. Constraint checks
• All flops are clocked or not
• There should not be unconstraint paths
• Input and output delays
Goals of Floorplanning:
A good floorplanning should meet the following constrains.
•Minimize the total chip area
•Make routing phase easy (routable)
•Improve the performance by reducing signal delays.
Inputs for floorplan:
- Netlist (.v/ .vhd/ .edif)
- Physical Libraries (.lef)
- Timing Libraries (.lib)
- Technology Files
- Constraints (.sdc)
Core area is approximately calculated by the tool from the Netlist
Note: LEF and Lib files need to be loaded before importing the design
Output of floorplan:
- Die/Block area
- I/O pad/placed
- Macro placed
- Power grid design
- Power pre-routing
Steps in Floorplan
- Initialize with Chip & Core Aspect Ratio (AR)
- Initialize with Core Utilization
- Initialize Row Configuration & Cell Orientation
- Provide the Core to Pad/ IO spacing (Core to IO clearance)
- Pins/ Pads Placement
- Macro Placement by Fly-line Analysis
- Macro Placement requirements are also need to consider
- Blockage Management (Placement/ Routing)
IO Placement
- Chip Level its IO Pads and Block Level its IO Pins
- Pin is a logical entity and is a property of a Port
- Port is a physical entity and a Port have only 1 Pin associated with it
- Netlist will have Pins and Layout will have Ports
- Unplaced Port is not represented in the Layout
Floorplan Qualification:
- No I/O ports short
- All I/O ports should be placed in routing grid
- All macros in placement grid
- No macros overlapping
- Check PG connections (For macros & pre-placed cells only)
- All the macros should be placed at the boundary
- There should not be any notches. If unavoidable, proper blockages has to be added
- Remove all unnecessary placement blockages & routing blockages (which might be put during floor-plan & pre-placing)