Intel Interview Questions for Mtech students

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  1. Internship project details. Asked in detail about the concept and implementation part. What’s special you did in this ?
  2. Can you tell me the list of courses you had in Masters?
  3. Virtuoso related basic question
  4. Counters- Synchronous vs Asynchronous – Very detailed – Asked some of the counters to design from FSM [gave me 15 min to finish ]
  5. Digital Design Concepts – all basics revised during this question
  6. Power Gating : Fine grain , coarse grain : details
  7. Latch based timing analysis concepts
  8. Detailed timing related questions: setup hold, cross talk, MCP, FP & asked to solve some of the reg 2 reg paths for setup time slack [given most of the parameters like flop setup req, clk per, uncertainity etc..]
  9. MOSFET vs BJT – some basics
  10. Adders – Half Adder, Full Adder, CLA, CSA & Ripple Carry Adder. Pros and Cons of each and which is preferred in what kind of scenarios ?
  11. MOSFET operation in detail
  12. Can you draw a latch at ckt level – at mos level ? And explain how does it work as a latch ?
  13. CMOS power consumption details : diff types and how to avoid each ?
  14. NOR gate operation at MOS level details ?
  15. NAND, NOR related questions- Why NAND is preferred ?
  16. Power gating, clock gating concepts – details and why these are used ?
  17. Some questions based on RESUME
  18. Setup, HOLD concepts using a latch internal mos structure ? Why there is need for these checks – can you explain the conceptual reason?
  19. FSMs- Melay vs Moore . Async vs Sync details
    1. In FSMs how timing is being affected ? How to counterattack this ?
  20. Register insertion, retiming concepts to avoid timing viol ?
  21. Do you know the latest trend on metal layers on a chip ? Can u guess the number of layers at 14nm used? – horizontal or vertical or mixed why ?
  22. Front End design Flow [I worked as intern in logic design team, so are the questions]
  23. RTL to Netlist – Design Compiler/ Synthesis Role ?
  24. Logic Optimization related questions – some K-MAP problems
  25. Formal Verification – Basic concepts
  26. What is the need to do FV ? [does that mean DC causes errors? ] [ what are the possible scenarios where Synthesis flow can cause issues ? ]
  27. Masters project
  28. DC topographical vs WLM concepts?
  29. PD flow -floorplan to chip finish – only explain the flow from netlist to GDS
  30. Latch vs FlipFlop- details. Which is best design element in terms of what?
  31. Why are latches preferred in CPU design world? Why? Can you relate it to time borrowing?
  32. If you have only one choice to fix only one of the last-minute timing violation, which one do you prefer and why?  Assume that there is one setup and one hold violation

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