VLSI Interview questions and answers
31. Aspect ratio?
It is nothing but width/Height: Width should be less, and height should be more each and every time. Aspect ratio should be less then 1.
32. What is halo? How it is different from all blockages?
Halo is a placement blockage which be applied around the macros. Its like hard that will not allow any std cells, macro, invertors & buffers.
When the macro will move so halo blockage will also move, in this way they are different from hard blockage.
33. Is there any thumb rule to port assignment to different layers?
Top metal layers will be using for power because the resistance will be low for that reason will be using top metal layer.
Then rest some layers use for clock and lower metal layer we will be using for macro, std cells usually.
34. Can we place macro in die area with reasons?
We cannot place macro in die area if place will see the DRC violations only port will be place in die, except that nothing will place in die area.
35. If the Tap cells, End cap cells are not in fixed status?
These physical cells will be in fixed status If not then will see the Base DRC violation those should not be move once it placed.
Three types of status
Fixed status
Place status
Unplaced status
Fixed status: Cells will not move anywhere.
•Place status: we can move the cells
•Unplaced status: Our cells are not placed that are in not core area.
Fixed status cells we can move that cell to change their status in place status.
If any violation is coming because of physical cells and cells are in fixed status at that time will change their status in place status from fixed so that will be able to move that cells and will fix the violation.
36. Which cell is used in clock buffer hvt or lvt?
Different vt cells having different process variation, so this cause either over or under pessimism of buffer (inverter) delay used in the clock tree.
This may result either reduce clock frequency or setup violation. Hence it is not recommended to use different vt cells in the clock tree.
37. What is temperature inversion? Why HVT cells more prone to temperature inversion than LVT, SVT?
Temperature has its effect on two
•mobility of conductor and threshold voltage
•which one will dominate will depend on the supply voltage, if the supply is in the range which is comparable to Vt then threshold voltage effect is dominant whereas if the supply voltage is very large than Vt then mobility has the dominant effect.
•65nm and above the supply voltage was way higher than the Vt so the delay of cell was due to the mobility which increase in temperature the mobility decreases so delay increases.
•But at lower node supply voltage was comparable to Vt (Supply volt was decreased to take care of the leakage current at lower node) so now delay was more a function to Vt effect, with increase in temperature the Vt decrease so the device is faster (as the turn on voltage has reduced)
•now coming to your question on hvt cells more prone to inversion is correct as within hvt, lvt, svt when you plot the temperature vs the delay
•the hvt is the one which shows a lot of variation compared to others reason being
38. Why is the standard cell height fixed in then layout?
•The standard cells are pre-defined, pre characterized and pre verified cells, to be used in semi-custom design. Standard cells architecture is design based on cells height which is determine based on the number of tracks, beta ratio, pitch and transistor width.
• Often standard cells are available in single height and double height. The double height cells are the high density and are used for ultra-high-speed operation.
39. How do you say the clock tree is properly built?
•It depends on what all you need. The basic requirement is minimum clock insertion delay and minimum skew.
40. Why do some clocks display “IIII” instead of “IV” where 4 is meant to be?
•It was used to visually balance the dial.
•I – II – III – IIII
•V – VI – VII – VIII
•IX – X – XI – XII
•In this way you have three groups of four numbers, and the dial looks more balanced and less cluttered.
40. When should we increase the drive strength of the cells?
•When the drive of a gate is not enough to drive the output net in that case will increase the drive strength.
There are also some scenarios in which we can increase.
•When the delay of the gate is poor, you want to improve the delay.
•To improve the transition. When any timing violation is coming, To avoid the cross talk etc.