ASIC Physical Design questions and Answers
51. What is the macro?
•Macros are the memory cells. These IPs are designed by the some another team that is Analog layout, which can be used in floor plan stage of the design.
52. What do you mean by core margin??
•Core margin is nothing but giving space between core to io and core to die.
•We define core margin by Core to IO boundary or Core to Die boundary.
53. What are the orientation of the ROW in design?
•Rows can be defined with different orientation as R0, MX, R0/MX Flip and abut, etc.
•Usually we chose Bottom MX and Flip/Abut in design these days, Where power/ground(VDD/VSS) shared with up and bottom to avoid the area loss.
54. What will happen if we don’t set multicycle path for hold ?
•Let’s say that a multi cycle path setup of N was applied, if no explicit hold multi cycle path is set, the default hold check will be per formed at (N-1)th edge of destination clock.
55. What are the placement constraints?
• Guide, fence ,region
56. What is mmmc file and why we need it?
•MMMC analysis is very important to perform, so that the IC can work on different mode of PVT (Process, Voltage, and Temperature). The variations in PVT can insert extra delay in the circuits and due to this delay timing constraints may not be met. Thus the IC must be robustly checked for every process corners.
57. Which one is critical to fix setup or hold time ?
•Hold time is critical to fix if only one position is given.
•Because setup time can be fix by lowering the frequency operation on the failing paths but hold time can be fix only changing the PVT corners not changing the frequency.
58. How to calculate maximum operating frequency in the given circuit?
•In order to calculate max op freq. we can calculate by setup time equation. Find the max. combinational path and calculate time period, from that we can calculate the max freq.
•Tcq + Tcomb + Tset <= Tperiod
•Freq = 1/Tperiod
59. What is metastability?
•When there is setup and hold violations in any flip flop it enters in a state where its output is unpredictable, means it could be 0 or 1. this unpredictable state is called metastability.
•Metastabilty state dangerous to have, these can lead to chip failure.
60. What is MTBF (Mean Time Between Failure) ?
•It indicates how often the given design/ module can fail, means what is the average time to fail two successive failures.
•MTBF should be high as possible.
•MTBF reduces as sampling frequency increases.