PD Interview Questions and Answers Part 3

Questions 61 to 80

ASIC PD Questions with Answers

61. How to fix setup and hold violations?

a) setup fixes:

1. Upsize the cell
2. Swap the cells from HVT to LVT
3. Add buffer if net delay dominates the buffer delay
4. Pushing the Capture path
5. Pulling the launch
   path
   b) Hold fixes:
6. Down size the cell
7. Swap the cells from LVT to HVT
8. Add buffer at D-pin of the flip flop
9. Pushing the launch path
10. Pull the capture path

62. How many corners you worked?

I worked on 10 corners.

63. On which corner you will fix setup?

a) For setup I read rc_worst corner.

64. On which corner you will fix hold?

a) For hold I read rc_best corner.

65. How to fix setup and hold violations if the base layers are fixed?

a) Setup:

1. Increase the metal width.
2. Route with highest metal layers

b) Hold:

1. Detour the net.
2. Route with lower metal layers.

66. Detail explanation about SDC?

a) SDC ( synopsys design constraint
file) In SDC we have information
like :

1. Clock definitions

• create_clock -name {test_clk} -period 8.000 -waveform { 0.000
  4.000 } [list [get_ports {scan_clk}]]
• create_clock -name {my_clk} -period 4.000 -waveform { 0.000
  2.000 } [list [get_ports {clk}]]
• create_clock -name {my_clk_v0} -period 8.000 -waveform { 0.000 4.000 }
• create_generated_clock -name div_clk -source [get_ports {clk}]
  divide_by 2 [get_pins {clk_div_reg/Q}]

1. External input and output delays

• Set_input_delay 0.5 –clock {clk1} – add_delay –max/min –rise/fall [
  get_ports { input ports or internal pins} ]
• Set_output_delay 0.7 –clock {clk1} –add_delay –max/min –rise/fall [
  get_ports
  {output ports or internal pins} ]
• Set_load –max 2 [get_ports { io ports} ]
• Set_drive –max 3 [ get_ports { io ports } ]

1. Max drv’s

• Set_max_transition 0.25 [ get_ports { io} ]
• Set_max_capacitance 0.1 [get_ports { io} ]
• Set_max_fanout 40 [get_ports {io} ]

1. Path exceptions

• Set_min_delay
• Set_max_delay
• Set_multicycle_path 3 –from [get_clocks {launch clock}] –to [
  get_clocks { capture clock}] -setup
  Set_multicycle_path 2 –from [get_clocks {launch clock}] –to [
  get_clocks { capture clock}] -hold
• Set_false_path –from [get_clocks {clk}] –to [get_clocks {clk_v}]
• Set_clock_uncertainty 0.2 –from [get_clocks{clk}] –to [get_clocks {clk_v} ]

67. Explain PD flow?

a) Inputs to the PD are netlist(.v) , .sdc , .lef , .lib , captables, udf/cpf.

1. Performing sanity checks on input files. if all sanity checks are cleared then
   only we move further.
2. Floor planning :

• define core area dimensions, calculate utilization and aspect ratio then
• place IO ports then
• place macros by following macro guidelines then
• place physical cells

1. placement :

• Global placement : std cells are placed based on hierarchy
• Placement optimization: scan chain reordering, HFNS, congestion
  fixing , timing optimization, area optimization, power optimization.

Detailed placement: In detailed placement all cells placed in a
legalized manner.

• Early global route. To analyse congestion and timing after placement
  stage.

1. CTS (clock tree synthesis):
   In CTS clock will be built form clock port to all flip flop clock pins. And then
   clock tree optimizations will be done
2. Routing:

• Global route: Tool try to finds shortest paths and assigns metal layers to it.
• Track assignment: In track assignment each net will be assigned on track.
• Detailed route: physical connections will be formed by using search and
  repair algorithm.

68. After placement what will you check?

• congestion
• timing ( drv’s and setup)
• core area utilization
• Cells placed in a legalized manner or not.

69. What are the inputs for placement?

• netlist (.v)
• sdc
• lef
• def
• lib

70. After CTS what will you check?

• skew and insertion delay (SOURCE LATENCY)
• timing (drv’s , setup and hold)
• congestion
• core area utilization
• cell legality