Questions 81 to 100
ASIC PD Interview Questions
81. what is cross talk?
Cross talk is the transfer of a voltage transition from multiple switching net (aggressor) to another static or switching net (victim) through a capacitor.
82. What is Electromigration?
Electron migration: The gradual displacement of metal atoms along with the charge
carriers due to the flow of high density current is called electron migration.
It results in shorts and opens in the circuit. To overcome EM increase the width of the metal
layers.
83. How many clocks you used?
a) There are 3 clocks in my design. One is main clock, test clock and generated clock.
84. How many power domains you have?
a) I did one project on Low power design. In that 3 power domains are there.
Two are switchable and one is always-on domain.
85. You worked on 28nm and 14nm technology, what differences you found?
No.of metal layers are increased from 28nm to 14nm.
Cross talk issues are more.
DRC rules are increased.
86. why we use .sdc file in placement?
a) After placement we will check setup violations, so while calculating timing from in-to-reg
and reg- to-out paths it requires external input and output delays those are mentioned in sdc
file. And also any path exceptions like multicycle path, false path and asynchronous paths.
And clock definitions are required for calculating timing.
87. what you will do in floorplan?
a) Floor planning :
place physical cells
define core area dimensions, calculate utilization and aspect ratio then
place IO ports then
place macros by following macro guidelines
88. Draw your block?
89. In between macros std cells can we place?
a) At placement stage if any std cells are placed in macro channel, if we didn’t get any
congestion issues then we can place. if we are getting congestion in macro channel then
put any hard blockage to avoid std cells placement.
90. what are the preplacement cells in your design?
In floorplan stage only Endcap cells and Welltap cells are placed.