91. How many clocks you have ? location of clocks? Frequency of design?
Three clocks are there in my design. IO ports are placed on top side of the block.
Frequency is 500 MHz.
92. What you know about ECO?
After post route stage, the routed netlist is sent to all sign off stages. At sign off stage if they found any timing, IR, lec and DRC’s related issues, then sign off people wrote some ECO’s (engineering change order) to solve those issues and send back to the PD people.
93. What is the relation between STA and PD?
In Physical design flow after Placement, CTS and Routing stage the STA people will involve to solve timing violations (DRV’S, setup and hold).
94. What will you do in CTS?
a) Before running CTS , we should provide some constraints like
- Specifying NDR’s (Non default routing rules) 2w2s
- Specifying routing layers
- Specifying Skew and insertion delay targets
- Specifying clock buffers and clock inverters list
- Clock exceptions
- Clock grouping
- DRV targets
The main targets of CTS are to balancing skew and insertion delay. In CTS stage ,
clock will be built from clock port to all flip flop clock pins. And then clock tree
optimization will be done.
95. what is the use of clock buffers and clock inverters?
clock buffers and clock inverters have equal rise and fall delays.
96. Which one you will prefer?
In my project I used both clock inverters and clock buffers. Clock inverter has good trans compared to clock buffers.
97. What do you mean by PBA?
PBA (path base analysis) while calculating timing, tool will follow path base analysis. In path base analysis tool pick worst delay arc while calculating setup and min delay arc for the cells while calculating hold irrespective of the path.
98. Draw your block? Where the pins are located? Which metal layers are used for your
pins?
pins located at top side of the block. Metal 4 is used for pins.
99. why you placed pins on top side , why not any other side?
a) The IO ports location purely depends on data flow. Based on communication on top
level chip, our block communication with other blocks will decides the port location.
100. What are the inputs of STA?
- netlist (.v)
- sdc
- lib
- spef