Questions 101 to 120
101. Tell me flow RTL onwards?
102. What is meant by empty modules?
For module, it has module definition and endmodule. It doesn’t contain logic inside it.
103. Difference between HVT and LVT cells by transistor level?
a) LVT Cells has Low threshold voltage and high doping concentration, therefore less
delay and more leakage power.
HVT Cells has High threshold voltage and less doping concentration, therefore more
delay and less leakage power.
104. . What consists of uncertainty where you’re getting those values? Why we need to
give those?
a) Pre CTS stage:
Uncertainty = skew + jitter + design
margin After CTS stage:
Uncertainty = jitter + design margin
We can get this value from top level people. To over constraint the design we consider
uncertainty parameters.
105. Explain PD inputs?
a) PD inputs are : netlist, sdc, lef, lib and captables, cpf/upf.
- Netlist : It contains the logical connectivity of the design. It contains Hierarchy
information , module info , input and output pins info , wire info, instance info. - SDC : It contains clock definitions , input and output delays , DRV’S and path
exceptions. - LEF : There are two types of lef’s. 1. Technology lef 2. Cell lef.
Technology lef contains physical information of all metal layers in the
design. Cell lef contains physical information of the cells. - LIB : It contains PVT information , power information (leakage and internal/short
circuit power) , cell functionality and cell timing information. - Captables : It contains resistance and capacitance values for the metal layers
based on different width and spacing and different capacitors ( coupling
capacitance , fringe capacitance etc) - CPF (Common power format): It contains power domain creation , operating
conditions of the domains , low power cell (isolation , level shifter, switch cell,
retension flop , always on buffer) rules.
105. What happens if lib and .v missing?
a) ERROR: (IMPIMEX-3): There is no verilog netlist found in init_verilog. The
variable is either not specified or specified incorrectly. Check the location of Verilog
file in the global file.
If netlist is missing tool won’t load the design.
106. What happens if lef and lib missing?
a) It loads the netlist. But shows errors like LIB missing: The design has been initialized in physical-only mode because the init_mmmc_file global variable was not defined.
Timing analysis will not be possible within this session. You can only use commands that do not depend on timing data. If you need to use timing, you need to restart with an init_mmmc_file to define the timing setup, or you can save this design and use restoreDesign – mmmc_file to add the timing setup information.
LEF missing: ERROR: (IMPEXT-3466): The technology layer information is not available. This can happen if either no LEF file is imported, or an error occurs while reading the LEF file(s). The capacitance table file cannot be read without the layer information.
106. Explain sanity checks?
a) checkNetlist : The checkNetlist command will check the netlist , is it have any :
- Tri-state buffers
- Multi driven Nets
- Combinational loops
- No.of input floating’s
- Empty modules
checkDesign –timingLibrary: This command is used to check the library. It shows errors like, - Cells with missing timing information
checkDesign –physicalLibrary : This command is used to check the LEF file. It shows errors
like, - cells with missing PG pin information , ( it shows information related to missing
physical information)
check_timing : This command is used to check the SDC. - No clock or clock is ideal
- No input delay
- Unconstrained endpoints
- No drive assertion
timeDesign –preplace : This command is used to check the timing violations present in the
design at synthesis stage only.
107. What happens if I have multi driven nets in my design?
Due to multi driven nets functionality will damage. Here we don’t know that which
value the buffer will drive. Multi driven nets should not be present in the design.
108. How will you place macros if you have 100 macros in your design?
a) By using design browser, we can group the macros of same hierarchy, and then we
will assign different colors to different hierarchies for easy identification. Then we will
place particular hierarchy of macros at one place by following fly line analysis.
109. Explain how power will be supplied to macros and stripes?
The stripes will get power from power rings. And the macros will get power from stripes.
Generally, for power stripes we will use higher metal layers (M8, M9) but macro pins are on
M3, M4, M5, M6 layers, so there should be stacked via from via3 to via9 to connect stripe
to macro pin.
110. Why setup violation occurs in placement stage?
In placement stage clock is ideal that means the skew is zero. Setup slack is difference of
required path and arrival path. Setup slack = RT – AT. If RT value is less compared to AT
value then we get the setup violation.
In placement stage clock is ideal so less delay is present in clock path, so we get setup violations.