VLSI Physical Design Questions
111. Why hold violation is not done at placement stage?
Because clock tree is not build at placement stage that means clock is ideal. Clock ideal
means, skew is zero, so we can’t get hold violations.
112. Explain macro guidelines?
- If you don’t have reasonable rationale to place the macro inside the core area,
then place macros around the chip periphery. - Communicating macros should be placed closure to each other.
- If macro is communicating with IO ports then place macro near to IO ports.
- Maintain proper channel spacing between macros.
- Avoid criss cross connections.
- Don’t rotate the macros but we can flip the macros.
113. Why should we not place macros at the center of the core area?
Placing a macro center of the core can invite serious consequence during routing due
to a lot of detour routing, because macros are equal to a large obstacle for routing.
Another advantage to placing the hard macros around the core periphery is it’s easier to
supply power to them, and reduces the change of IR drop problems to macros consuming
high amounts of power.
114. Have you fixed skew? If so how?
I didn’t fixed skew. But I know how to fix skew i.e we should concentrate on each path
while fixing skew because if you fix skew for one path then any other path gets violated.
Fixing skew is nothing but adding buffers and removing buffers in the clock path.
115. What is ECO flow?
- load the routed data base
- remove filler cells
- source ECO file
- ecoPlace
- ecoRoute
- add filler cells
- generate spef
- send this data base to the sign off stages
116. What are all sign off tools you have experience?
I have hands on experience on PD tool only. I don’t have hands on experience on sign off
tools.
117. what are half cycle paths? In half cycle path which one is critical? Setup or hold?
A path which requires only half cycle to capture the data. It is formed when data is
launched on positive edge of the clock and captured on negative edge of the clock or when
data gets launched on negative edge of the clock and gets captured on positive edge of the
clock.
In such paths, setup check become more tight as setup gets only half cycle while hold
constraint is relaxed by half cycle.
The falling edge occurs at 5ns and the rising edge occurs at 10ns. Thus, the data gets only a
half-cycle, which is 5ns, to propagate to the capture flip-flop. While the data path gets
only half- cycle for setup check, an extra half-cycle is available for the hold timing check.
The hold check always occurs one cycle prior to the capture edge. Since the capture edge
occurs at 10ns, the previous capture edge is at 0ns, and hence the hold gets checked at 0ns.
This effectively adds a half-cycle margin for hold checking and thus results in a large positive
slack on hold.
118. If you are facing congestion globally ,what is the reason for that?
The reason maybe bad floorplan.
119. After CTS optimization how you will fix hold?
By skewing the clock path we will fix the timing violations. Hold can be fixed by
pushing (adding buffers) launch path and pulling (removing buffers) the capture path.
120. What is ICG? What is the advantage of ICG?
Clock gating is a very common technique to save power by stopping the clock to a module
when the module is not operating. The advantage of ICG cell is , it reduces dynamic power
consumption.
