Global Variations
These are PVT variations that depend on external factors like Process, Supply Voltage and Temperature.
ICs are fabricated in batches and hence exhibit die to die variations. Some exhibit strong process (fast switching) and weak process (slow switching). These are known as inter-chip variations.
Local Variations
Local variations are also variations in PVT, but these are intra-chip variations known as OCV
Process:
All the transistors in a chip cannot be expected to have the same process. There can be variations in channel length, oxide thickness, doping concentration, metal thickness etc due to imperfections in manufacturing process like mask print, etching etc.
Voltage:
The supply voltage reaching the power pins will not be the same for all standard cells. The power network has a finite resistance.
Consider two cells, one which is placed closer, and other placed far. As the interconnect length for the farther cell is more, it has more resistance and results in a higher IR drop, thereby reducing the supply voltage reaching the cell.
As the voltage is less, this cell has more delay than the cell which is placed closer.
Temperature:
The transistor density within a chip is not uniform. Some regions of the chip have higher density and higher switching, resulting in a higher power dissipation. Hence the junction temperature at these regions is higher forming localized hot spots.
This variation in temperature across the chip can result in different delays
How do we account OCV variations?
As a result of OCV, some cells may be fast or slow than expected. If these variations are not
accounted, results may be pessimistic and can lead to setup or hold violations.
In order to model these, we introduce derates. Timing derates are multiplied with the net delay and
cell delay for the launch and capture clock paths.
Let us consider a timing derate of 8% and how it is accounted in setup and hold analysis
Setup analysis:
Setup check is done in worst case. The setup check is more pessimistic when the launch clock reaches
late than the capture clock. Here we multiply the launch path delays with late derate of 1.08 and the capture path delays with an early derate of 0.92
Hold analysis:
Hold check is done in best case. Hold check is more pessimistic when the launch clock reaches early
than the capture clock.
Here we multiply the launch path delays with an early derate of 0.92, and
capture path delays with a late derate of 1.08
OCV – Sources of variation :- Etching
Sample example of inverter layout and it’s also showing the “W” and “L” parameter
Lets look at the chain of inverters to understand the impact of etching
But the ideal scenario is
Photo lithography fabrication technique to build the inverters on silicon wafer and it’s the non-ideal process, where edges will not exactly be straight lines but there will be disturbances
Etching impact on transistors
This variation also dependent on what kind of logic cell which is present on the either side of this inverter
If it’s surrounded by chain of inverters on either side, the variation on the sides will be less as the process parameters to build mask for a chain of similar size inverter, is almost the same.
But, if the inverters are surrounded by other gates, like flip flops, then the variation will be more
W/L changes it changes on drain current
OCV – Sources of variation :-oxide thickness
Ideal deposition of oxide layer
Gate oxide variation
Oxide thickness impacting on your drain current in turn it impacts on the cell delay characterization
Process variation on propagation delay
