PVT Variations
PVT:
PVT is abbreviation for Process, Voltage and Temperature.
In order to make our chip to work in
all possible conditions, like it should work in Siachen Glacier at -40°C and also in Sahara Desert at
60°C, we simulate it at different corners of process, voltage and temperature which IC may face
after fabrication.
These conditions are called as corners. All these three parameters affect the
delay of the cell. We will see each and every parameter and its effect on delay in detail.
What is process?
Process variation is the deviation in attributes of transistor during the fabrication.
During manufacturing a die, the area at the center and that at the boundary will have different
process variation. This happens because layers which will be getting fabricated cannot be
uniform all over the die.
As we go away from the center of the die, layers can differ in their sizes.
Process variation is gradual. It cannot be abrupt
Factors causing process variation
- Wavelength of UV light
- Manufacturing defects
- Oxide thickness variation
- Dopant and mobility fluctuation
- Transistor width, length etc.
- RC Variation
How process affects delay?
Process variations will cause the parameters like threshold voltage to change its value from
expected.
Threshold voltage depends on oxide thickness, source-to-body voltage and implant
impurities. Consider the drain current equation for NMOS.
Current flowing through the channel directly depends upon mobility (μn),
oxide capacitance Cox
Delay variation with respect to voltage
Possible reasons for voltage variation
- Supply voltage fluctuations :- It’s IR drop, IR drop is caused by the current flow over the
parasitic resistance of the power grid. IR drop reduces the supply voltage from the required
value. - Supply noise:- Voltage drop/Overshoot due to fluctuation in
inductance, resistance & capacitance - Voltage variation across voltage regulators/Power supply ports
Delay variation with respect to temperature
The temperature at the junction inside the chip can vary within a big range and that’s why
temperature variation need to be considered.
Delay of a cell increases with increase in temperature. But this is not true for all technology nodes. For deep sub-micron technologies this behavior is contrary. This phenomenon is called as temperature inversion.
What is Temperature Inversion?
The delay depends on the output capacitance and ID current (directly proportional to Cout and
inversely proportional to ID). When the temperature increases, delay also increases (due to the
variation in carrier concentration and mobility)
But when temperature decreases, delay variation shows different characteristics for submicron
technologies.
For technology nodes below 65nm, the delay will increase with decrease in
temperature and it will be maximum at -40°C. This phenomena is known as “temperature
inversion”
As temperature increases, mobility and threshold voltage start decreasing. The delay is
inversely proportional to the mobility and directly proportional to the threshold voltage.
So the resultant effect from both mobility and threshold voltage decides the value of delay.
Consider the current equation of a MOSFET for better understanding
In the higher technology node, where the supply voltage is very high, the effect of VTh is very
low as (VGS– VTh) value is large.
Hence mobility plays major role in deciding current. So at higher technology nodes, when the temperature increases mobility decreases and as a result the delay will increase.
At the lower technology node (specifically, less than 65nm), the supply voltage is very low, so
the (VGS– VTh) difference is small and the square of this value is very small resulting reduced
ID current, which increases delay at lower temperature.
Where at other end above 65nm delay decreases at lower temperature