Synthesis

What is Synthesis?

 

 

The process of converting HDL design (Verilog or System Verilog) into a gate-level netlist is called synthesis.

 

 

Types of Synthesis:

 

 

 

1. 1. Logical Synthesis

 

 

1. 1. Physical Synthesis

 

 

 

Logical Synthesis:

 

 

Inputs required for Logical Synthesis:

 

 

 

• • RTL

 

 

• • SDC

 

 

• • LIB

 

 

• • LEF

 

 

• • Technology file (.tf)

 

 

 

The tool maps the RTL to the technology dependent gates, it also optimizes the design based on the constraints defined in the .sdc file.

 

 

Physical Synthesis:

 

 

In Physical Synthesis in addition to the inputs mentioned in Logical Synthesis, Floorplan DEF is included. This gives the tool some idea about the placement of the memories and standard cells in the design, By using these, the tool optimizes the design much better.

 

 

In the next post, we will discuss synthesis flow related to the tool.