UPF offers a comprehensive set of features that enable designers to effectively manage power intent throughout the design process, ensuring efficient power consumption and optimization.
What is a Power Domain?
Power domains are distinct regions within a chip that have separate power and ground networks. They allow different sections of the design to operate at varying power levels, optimizing power consumption. UPF provides a hierarchical structure for defining power domains and their relationships.
What is a Hierarchy?
UPF supports a hierarchical representation of power domains, enabling designers to organize power intent according to the design’s functional blocks and sub-blocks.
Power States and Modes
Modern chips often operate in multiple power modes or states to balance performance and power consumption. UPF allows designers to specify these power modes, defining how the design transitions between them.
- Power Modes: UPF enables designers to describe various power modes, such as active mode, sleep mode, or standby mode. Each mode has its own power consumption characteristics.
- State Transitions: Designers can define conditions for transitioning between power states, ensuring smooth shifts in power modes based on factors like workload or user inputs.
Voltage area and Power area
Voltage and power area definitions in UPF are crucial for managing power and performance trade-offs. Different blocks within a design might operate at distinct voltage levels to achieve the right balance between performance and energy efficiency.
- Voltage Definitions: Designers can define voltage domains and their associated voltage levels. This allows for adaptive voltage scaling, where voltage levels can be adjusted based on workload.
- Power-Aware Synthesis: UPF’s voltage and power area definitions influence the synthesis process, helping the tools optimize the design’s performance and power consumption.
Lowe Power Cells
Isolation and Retention Strategies:
During low-power modes, certain blocks may need to be isolated to prevent unwanted interactions or leakage power. UPF facilitates the definition of isolation and retention strategies for power domains.
- Isolation Cells: UPF allows designers to specify isolation cells that are inserted between power domains to prevent unintended interactions during power transitions.
- Retention: Designers can define which state each flip-flop should retain during low-power modes, ensuring critical data isn’t lost.
Interface with EDA Tools:
UPF isn’t just a theoretical framework; it seamlessly integrates with Electronic Design Automation (EDA) tools to ensure that power intent is consistently carried forward throughout the design process.
- Synthesis: UPF guides the synthesis tools to optimize the design while adhering to the specified power intent, voltage levels, and power modes.
- Place and Route: During place and route, UPF helps ensure that power network connectivity, isolation cells, and other power-related features are accurately implemented.
What’s inside a UPF file ?
Power intent is defined using an extension of the Tool Command Language (Tcl) and has the following components:
- Power Domains
- Power Supply Network
- Power State Table
- Isolation Strategies
- Retention Strategies
- Level Shifter Strategies
- Repeater Strategies
Who creates UPF files?
IP vendors supply RTL code, and constraint UPF file, then the design team adds a configuration UPF file for the specific context. Implementation-specific UPF files are also added along the way, so the EDA tool flow becomes:
How about using hierarchy ?
UPF supports both flat and hierarchical descriptions, and in general it’s recommended to align power domains with your logic hierarchy to keep life simple. If you choose to implement your design from the bottom-up, then ports need to be added in your UPF descriptions.
In a traditional bottom-up methodology an engineer would read all of the UPF files, then start manually editing each UPF file to ready them for merging into a top file. The UPF top-level file would be manually created, with care made to verify that proper syntax was typed. The power rules would also be verified before and after promotion.
Here’s a diagram showing a simple chip design example with four instances, named A, B, C, D; and at the top-level you can describe this with either hierarchy (left side), or as a flat design (right side):
In the example on the left, there are five UPF files organized in a hierarchy. On the right, there’s only one UPF file in a simpler setup. Changing between using UPF hierarchy or a flat structure is like moving up or down and involves detailed editing using a tool called Tcl. You could do these edits by hand, hoping they’re all right, or you could use a special software tool designed for this job.
When you go from a single, flat UPF file to a collection of UPF files arranged hierarchically, it’s called moving down, and again, you have to edit things manually. If any changes are made to the RTL code during this process, it means more editing in the UPF files.