Technology Node
What is Node in VLSI? Smallest Half -Pitch of contacted Metal 1 lines [lowest metal in that process] that […]
PNR
DFT – Design For Testability
Design for Testability: The Need for Modern VLSI Design DFT is the acronym for Design for Testability. DFT is an important
DPT in Physical Design
What is Double Patterning? Double patterning is one of several advanced techniques used in the semiconductor industry to continue scaling
Design for Manufacturability (DFM)
Yield Classification Why DFM/DFY ? Need for DFM/DFY Importance of DFM/DFY DFM/DFY Solutions DFM: Recommendations Wire Spreading Metal Fill Hot
Max Transition Violation
When a signal takes too long transiting from one logic level to another, a transition violation is reported. The violation
Design Rule check in PV
Physical Design Verification What is DRC? DRC stands for Design Rule Check DRC: It is actually used for making sure
Placement in VLSI Physical Domain
VLSI Backend Pre-Placement Optimization Pre-Placement Optimization Goals Optimizations before Placement Zero-RC Optimization Note: Take care of don’t use cells while
Process Antenna Rule
fig(i) Process Antenna Effect Antenna Ratio Checks Antenna rules are defined in LEFs. These rules are different for metal layers and
Electromigration Causes and Fixes
Signal EM Failure Mechanism 1. Non-uniformity in lattice structure of Interconnects: There exists a non-uniformity of metal interconect structures during fabrication