Checks after each stage in Physical Design

What are all the things to check once floorplan is done

After the placement of macros and IOs, please do the following checks.

1. Are all the tap cells, end cap cells, spare cells, DCAP cells (at the intended locations if any) are placed as per the physical design requirement?
2. Channel spacing between the memories. Avoid constrictive edges.
3. Run DRC to check for plausible DRC’s like overlapping of endcap cells with that of macros can be identified and can be fixed at an earlier stage. Certain unique DRC checks are attributed to technology. For example, in 40nm, the poly orientation for all the SRAMs should be unidirectional. If you don’t place them accordingly, after going through PNR, you will end up in changing the floor planning.
4. Walk through the IO pins or IO pads. Ensure its order with the IO pinout sheets if any provided by the design team. If provided the DEF, then it wouldn’t be an issue. If you are doing an IO pin placement, group the bus bits, use double width for clock IO pins and make sure to leave double spacing on either of them.
5. With the observation from #4, you can position the placement of filler pads and power and ground pads accordingly. If the die is of flip chip type, then bumps will take care of it.
6. Run an early power analysis to keep track of the power grid resistance. You need not analyse the voltage drop since the design is not placed still based on connectivity and timing. But you can validate that the PG power grid is balanced, robust and will it provide a lesser instance voltage drop in any corner of the die. Also, you can add stripes wherever required before diving into the next stage.
7. Make sure the halos are around all blocks and placement blockages are at the intended locations. Apart from placement halos, you can use also routing halos to mitigate the signal integrity issues.
8. Check whether all the placement constraints like spacing between next cell/block, guard ring etc of all analog macros are satisfied. Carefully go through the documentation of all analog blocks and make sure you have followed all the physical implementation guidelines and floorplan considerations.
9. Resistance and capacitance estimation and routing constraints of analog custom routes should go side by side and if needed adjustments, should be taken during this step earlier.
10. Check whether the timing constraints and netlist are loaded with no errors. Make sure that the netlist is unique.
11. Go through the log file of this step run and grep for any errors/warnings.
12. Track the std cell utilization and adjust the die size if needed.
13. You can write out the timing reports and compare it with the STA reports. (Before PNR).

Checks after Placement:

1. Check the logs for any errors/warnings.
2. Check the transition time and setup time reports. If any paths are found to be false or if any constraints seem to be missing, discuss with the synthesis people so that they can update the constraints.
3. Check the legality of the design for any cell overlaps, illegal orientation etc.
4. Check the congestion map to see whether there is any local congestion in the channels or in the core area itself. Keep an eye on the over flow number which should be minimal. Also, a lot of such less overflow numbers clustered in a particular area leads to local congestion at a later stage. When going through both the statistical congestion reports and visual congestion map, you can better understand the congestion of the design.
5. Evaluate the reason for the congestion and do the fixes in the floorplan or identify the need for cell padding/partial placement blockage. Look at the hierarchical placement of std cells. Make sure that a single hierarchy is not split.
6. Look at the module level placement of cells and see if any bounds are required are clock/reset modules.
7. Make sure the scan chain re-ordering has happened.
8. Make sure the tluplus/qrc tech files are loaded properly.
9. Make sure that you have blocked clock cells so that it won’t be used in the data path optimization. It will could result in increase in area.
10. Make sure that all the don’t touch cells/network are respected by the tool. Dont touch list given by the DE team is applied properly.

Checks after Clock Tree Synthesis (CTS):

1. Again, check the logs for any errors/warnings.
2. After CTS, ensure that all the clock trees are balanced.
3. Look at the latency and skew for each clock group/skew group.
4. Make sure that there are no clock transition violations.
5. Make sure that there are no clustering of clock buffers/inverters in a single location that could leads to huge dynamic power consumption.
6. Check the clock NDR coverage.
7. Check whether the clock shielding is applied correctly and the shielding the coverage is close to 100%.
8. Check the double via coverage in the clock nets.
9. Usually, we will use a single type of vt std cells for building the clock tree to avoid the VT variation.
10. Track the std cell utilization and estimate the area increase. Estimate the number of clock inverters/buffers added are reasonable.
11. Make sure to convert all the normal cells in the clock path to equivalent clock cells if any. This gives the equal rise and fall time across the clock network.

Checks after Post CTS:

1. Provide the correct set of uncertainty and max transition constraint
2. In this step, hold optimization happens for the first time. The tool will try to add delay cells to fix the timing violations. If there are constraint issues, the tool will try to fix the unwanted timing paths.
3. Check the transition time, setup and hold timing reports
4. Track the std cell utilization and estimate the area increase.

Checks after Routing:

1. After routing, checkwhether there are any shorts or routes left opened.
2. Check for the double via coverage for yield enhancement.
3. Check all the timing related reports such as max trans, setup, hold etc.
4. If you see huge differences in the timing violation between pre and post stage, then there is definitely a correlation issue in RC factors.
5. Run a DRC at the GDS level to see if there are any specific violation that has a huge count ie. any via issues etc.
6. Run LVS at the GDS level to make sure that the design completely clean of shorts/opens. This will also somehow ensure that the IP integration at the top level is flawless.
7. Check whether any antenna violations or see the log whether post route antenna diode insertions are happened.