Solving Congestion with practical approach
What is Congestion in VLSI?
Congestion in VLSI (Very large-scale Integration) design refers to the circumstance when the number of routing tracks is less than the required routing tracks.
These routing resources are used to connect all the required wires between the different components of the design.
PnR tool highlights congested areas as red hotspots, as depicted in figure 1.
As the complexity of the design increases, congestion has become a major issue in chip design that requires careful consideration and optimization to ensure that the design meets the required timing, power, and area constraints.
Approaches and PnR Tool (ICC2)
Fig-1
Congestion report:
- GRC: The term GRC is an abbreviation of Global Routing Cells. During the initial placement, the core area gets divided into equally sized small squares called GRC.
- Overflow total: The summation of the total number of overflow routes for all GRCs. In the above report, it is 1,384,599.Overflow Max: “Both Dirs” means combined results for both horizontal and vertical routing directions.
- Max indicates the maximum number of overflow routes for a single GRC among all GRCs. For example, if there are 100 routing tracks available at a GRC while 172 tracks are going through it, that means the overflow is 72 for this GRC. Overflow (%): The GRCs value is the total number of global routing cells with any overflow/lack of routing resources.
- A GRC value of 426,013 indicates that 426,013 GRCs has an overflow among all GRCs. The overflow percentage (%) shows that out of the total number of GRCs, a certain percentage GRCs have overflow.
- In the congestion report:
- – The Overflow value is the total number of wires in the design global routing cells that do not have a corresponding track available.
- – The Max value corresponds to the highest number of over utilized wires in a single global routing cell.
- – The GRCs value is the total number of over congested global routing
Cause of congestion:
- Bad floorplan/inappropriate placement of macros.
- High standard cell density in a particular area.
- High number of standard cells in close vicinity of macros, as shown in Figure 4.
- Routing blockages over standard cells, as shown in Figure 2.
- High port density, as shown in Figure 3.
- Scan chain reordering and mixing/swapping are restricted.
- Improper optimization of netlist during synthesis.
Fig-2
Fig-3
Fig-4
Congestion alleviation Techniques:
- Placement blockages
- Cell padding
- Keep out margin/HALO.
- Modify PG grid.
- Congestion driven placement.
- Try different techniques during synthesis like logical synthesis, topographical synthesis.
- SPG and non-SPG placement.
- Refine placement/floorplan.
- Placement blockages: Spread the standard cells if they are highly dense by creating partial placement blockages, as shown in Figure 5.
- Alternatively, restrict the placement of standard cells in a particular area if there is an immense lack of routing resources by creating hard placement blockages, as shown in Figure 6.
- create_placement_blockage -type partial -blocked_percentage 50 -boundary {{llx lly} {urx ury}} -name Partial_PB
- create_placement_blockage -type hard -boundary { {lrx lry} {urx ury} } –name Hard_PB
Fig-5
Fig-6
Keep out margin/Halo: Keepout margin is a region around the boundary of a macro in which no other cells are placed.
Keeping the placement of cells out of such regions avoids congestion and net detouring and produces better Quality of result. In Figure –7, a keepout margin is created around the macro.
- create_keepout_margin -type hard -outer {5 5 5 5 } [get_cells *macro_name*]
Fig-7
Cell padding: Applying a keepout margin around standard cells is known as cell padding. When a cell has a high number of pins like a multibit flop, the demand for routing resources increases. Hence, we restrict the placement of cells near these cells to avoid congestion.
If we have more pin density, which can be reduced by adding cell-padding to the cells which is causing
congestion.
Cell padding can be applied by seeing the keep out margin command.
Implementing cell padding:
- create_keepout_margin -type hard -outer {3.9200 3.9200 3.9200 3.9200} [get_cells cell_name]
- Refine_opt/incremental placement.
Fig-8
Higher cell density can cause for congestion.
By default, the cell density can be upto 95%. We can reduce the cell density at congested areas by using coordinate option
ICC Command:
set_congestion_options – max_util 0.6 – coordinate {x1 y1 x2 y2}
set placer_max_cell_density_threshold 0.6 –> set the placement max density
Here we set the maximum cell density upto 60% and given the coordinates for the particular area
Congestion related variable:
- set_app_options -name place_opt.place.congestion_effort -value high
- set_app_options -name place.coarse.cong_restruct_effort -value ultra
- set_app_options -name place.coarse.congestion_layer_aware -value true
- Refine placement: The refine placement performs incremental congestion optimization for congested designs. One should perform this after detailed placement.refine_placement -effort high -congestion_effort high