Once we start working on low power design, we need to perform low power checks
That includes
Reading the PG netlist
Reading the UPF
Run low power checks called CLP
Make sure IN ICC your check_mv_design is clean
Chevk_mv_design:
- To verify the power network definition for a multivoltage design, run the check_mv_design command.
- This command checks for various types of violations such as inconsistent and conflicting library settings, missing isolation cells, and incorrect voltage shifting across power domains. •
- To check the power and ground connections, use the -power_connectivity option.
- When you use this option, the tool checks the power and ground connections in addition to the power network definition, and updates the connections if it finds any issues. By default, it does not check the power and ground connections.
- To specify the maximum number of messages for each violation type, use the -max_message_count option. By default, it reports a only 20 occurrences of a given violation type
Types of low power checks
Static Checks
- Static checks detect architectural issues in the design.
- As a missing isolation or level shifter cell.
- Can be performed without running a simulation
- Save time and effort as you do not need to write a testbench. So you can run them on your low-power design as soon as the design is readyThere are two kinds of static checks: static RTL and static gate-level simulation (GLS) checks. The static RTL checks are run on RTL designs and static GLS checks on gate-level design
Dynamic checks : Dynamic checks are performed on the design while running simulation. Dynamic checks detect behavioral issues in the design, such as incorrect power sequencing of power domains
Isolation cells
Isolation cells are additional cells inserted by the synthesis tools for isolating the buses/wires crossing from power-gated domain of a circuit to its always-on domain.
They clamp the output node to a known voltage.
In the isolation list we specify the clamping value of the nets as logic 0 or logic 1 and accordingly the synthesis tool will insert isolation cells.
Level Shifter Cells
Level Shifters (LS) are special standard cells used in Multi Voltage designs to covert one voltage level to another.
As Multi Voltage designs have more than one voltage domain, level shifters are used for all the signals crossing from one voltage domain to another voltage domain.
Like isolation cells, level shifters are inserted by the synthesis tool
Low to High Level Shifters
Low to High LS are used for signals crossing from a lower voltage domain to higher voltage domain.
It basically amplifies the source signal so that it can be interpreted properly in the destination domain.
Suppose a 0.7V signal is crossing from 0.7V voltage domain to 1.0V voltage domain.
Now in the lower voltage domain it corresponds to logic-1 but in higher voltage domain it is neither logic-1 nor logic-0, so the signal becomes unknown (or ‘X’) in the absence of Low to High LS.
High to Low Level Shifters
High to Low LS are used for signals crossing from higher voltage domain to lower voltage domain.
It basically attenuates the source signal.
Although putting a LS for signals crossing from higher voltage domain to lower voltage domain is optional as signals will be interpreted properly in destination domain, but typically we put a LS to avoid stress on the transistors of lower voltage domain due to high voltage of the source signal.
Bi-directional Level Shifters
When dynamic voltage scaling or dynamic voltage frequency scaling is used the voltage relation between the source and destination might change over time of operation. In that case we need level shifter which is capable of shifting both low to high voltage signals and high to low voltage signals.
Retention cells
These cells are special flops with multiple power supply. They are typically used as a shadow register to retain its value even if the block in which its residing is shut-down.
All the paths leading to this register need to be ‘always_on’ and hence special care must be taken to synthesize/place/route them.
In a nut-shell, “When design blocks are switched off for sleep mode, data in all flip-flops contained within the block will be lost. If the designer desires to retain state, retention flip-flops must be used”.
The retention flop has the same structure as a standard master-slave flop.
However, the retention flop has a balloon latch that is connected to true-Vdd.
With the proper series of control signals before sleep, the data in the flop can be written into the balloon latch.
Similarly, when the block comes out of sleep, the data can be written back into the flip-flop
What are all the low power checks?
Back-to-Back Checks
- Sometimes your design has back-to-back cells, which might be any of the following types:
- Isolation and level shifter cell
- Level shifter and isolation cell
- Isolation and isolation cell
- Level shifter and level shifter cell
Other checks
- The design cells have missing liberty attributes.
- The isolation, level shifter, or retention supply is powered-down during the active isolation, level shifting, or retention period.
- The power signal of a power domain gets corrupted.
- The input of a power domain toggles when the power domain is powered-down.
- The power state table or the supply port reaches an illegal or undefined state.