Placement stages in Physical Design

In this stage, all the standard cells are placed in the design (size, shape & macro-placement is done in floorplan). Placement will be driven by different criteria like timing driven, congestion driven, power optimization etc. Timing & Routing convergence depends a lot on quality of placement

What are all the inputs for placement?

• Technology file (.tf )
• Netlist
• SDC
• Library files (.lib & .lef) &
• TLU+ file
• Floorplan & Powerplan DEF file

Objectives of Placement

Timing, Power and Area optimizations

Minimum congestion

Minimal cell density, pin density and congestion hot-spots

Minimal timing DRVs

6 Different Stages of Placement

1. Pre-placement: Placing the cells before asking the tool to place all the std cells. There are few std cells which needs to be placed across the core area to meet the founder requirement. End-cap cells, tap-cells, I/O buffers, spare cells etc… are pre-placed cells
2. Coarse Placement: Initial fast placement of std cells without logical optimization on. Makes a good seed for further placement. Some cells may not be legally placed and there can be overlapping.
3. Placement Legalization: To avoid overlapping cells need to have legalized locations. Overlapping cells cannot be fabricated, creates shorts etc…
4. HFNS: (High Fanout Net Synthesis) All high fan-out nets will be synthesized (buffer tree) except clock nets & nets with don’t touch attribute. Scan-enable and reset are few examples of high fan-out nets. HFNS honors max fan-out setting.
   HFNs is the process of buffering the high fan-out nets to balance the load. Too many load affects delay numbers and transition times because load is directly proportional to the delay. BY buffering the HFN the load can be balanced. This is called HFNs.
5. Timing/Power Optimizations: It includes cell sizing, cloning, buffer insertion, area recovery etc…
6. Scan chain reordering: DFT tool flow makes a list of all the scan-able flops in the design, and sorts them based on their hierarchy. In APR tool scan chains are reordered on the basis of placement of flops & Q-SI routing. This is nothing but scan-chain reordering. Scan-chain reordering helps to reduce congestion, total wire-length etc

What is a Good Placement?

• Unplaced cells (should be 0)
• Cells overlap (should be 0)
• Utilization (Value shouldn’t increase more)
• Minimal timing issue
• Minimal congestion issue
• Minimal timing DRVs
• Total area after optimization shouldn’t have much increase

Outputs of Placement

Congestion report

Timing report

Design with all std cells placed in core area

Placement DEF file