Avoiding Clock Tree Synthesis (CTS) Pitfalls.
Here, some common problems are discussed that many design engineers today face when they try
to run CTS.
The suggestions and steps you can take to avoid these problems are discussed.
It is always a good idea to invest the time at the beginning to understand the clock structure and
the clock gating in your design.
You should also know where your gating elements are placed and the topology of your floor plan
including the location of sync points.
That will ensure that you are building clock trees that will give you good timing results. This
knowledge will also help you make clock tree decisions that will help CTS build better quality
clock trees.
The following list provides suggestions for dealing with problems you may encounter.
A. Big insertion delays.
Some of the things you can check if you have big insertion delays are:
11 Important points to take note of in CTS:
- Are there delay cells in the design?
Check to see if there are delay cells in the netlist that are present in the current
design. These could be causing delay that cannot be optimized and CTS is building
clock trees which match all other paths to this worst insertion delay.
2. Are there cells marked “don’t touch” in the design?
There could be cells in the design that are marked “dont touch” which prevents CTS
from deleting them and building optimal clock trees.
- Can the floor-plan be modified to be more clocks friendly?
Sometimes it helps to consider CTS (and timing) as a constraint for floor-planning.
Long skinny channels leading to more long skinny placement channels will give both
timing optimization and CTS problems.
Consider using soft blockages or refloorplan.
4. Can you define new create_clocks that will assist CTS (divide and rule)?
Many times running CTS on the main clock pin is not the optimal way to build clock
trees. It may help to divide the clock tree based on the floorplan and the syncpins and
build sub clocks, then define the sync pins and build the upper main clock.
5. Are the syncPins defined correctly for macros?
It is a good idea to check the syncPins file to see if the sync pins make sense. Also
check that the numbers are accurate and that the time units are correct.
6. If there are ignore pins in the design are they defined as ignore pins?
If there are ignore pins in the design, make sure you define these as ignore pins
before running CTS.
. 7. Have you used varRouteRules and propogated by astMarckClockTree?
Defining varRouteRules helps to reduce the insertion delay.
Define shielding, and double or more width rules for clock nets,
and propagate them using astMarkClockTree.
8. Are the CTU buffers marked as “dont use”?
Some technologies use clock tree buffers. Make sure you are using these only for
your clock tree. Also make sure they are not marked “dont use”.
9. Be creative and use different CTS intParams to get better results.
There are several CTS options in the form that you can try to change to get better or
more desireable CTS results.
10. Use inverters only to build the clock tree if possible.
11. Define variable route rules with greater than default widths and clearance
and also shield the clock nets. Then propagate these rules using
astMarkClockTree. This will help insertion delay.