In the Physical design flow, Power planning is done once floorplanning gets completed.
The idea here is to supply power througout the design.
Types of Power Planning
- core cell power management
- I/O cell power management
In core cell power management VDD and VSS power rings
are formed around the core and macro. In addition to this straps and trunks are created for macros
as per the power requirement.
In I/O cell power management, power rings are formed for I/O
cells and trunks are constructed between core power ring and power pads. Top to bottom
approach is used for the power analysis
Rings
Carries VDD and VSS around the chip
Stripes
Carries VDD and VSS from Rings across the chip
Rails
Connect VDD and VSS to the standard cell VDD and VSS.
2 methods of Power supply
Wirebond power supply
In wire bounded only the edges can be used.
Disadvantage:
- More IR drop
- Less Speed, needs more die area for IO limited design.
Flip-chip Power supply
Advantage:
- Small IR drop
- Very high speed design possible
Disadvantage:
- Heat sink problem
- Cost of flip-chip packing is more.
- Less reliable than wirebond.
Flip-Chip Basics
Flip the die upside down and the whole surface can be connected to package in principle.
- Opportunity to add voltage sources to the core regions- but must have adequate ESD protection
- Opportunity to reduce die size (less core supply cells in the IO ring; less IO PG supply cells in the IO ring; IO cells could be abutted)
- The bumping process can be expensive
- The substrate routing problem is more difficult (binding posts have larger separation than bump pads) A more expensive substrate may be required
- The Package can in principle be same size as the die
- Potentially faster operation as wire bond inductance is avoided.
Two types of flipchips being designed currently.
Peripheral IO flipchip.
Area IO flipchip.
Peripheral IO flipchip
Most IO cells remain in a conventional ring
IO cells can be abutted in Single Rows of IO cells
Dual Rows of IO cells can also be used
IO cells connect to bump pads via the redistribution layer (RDL). From bump pads we connect to bumps and then the package.
Limited benefits in terms of die size reduction
It may be possible to add core PG voltages directly to the core region. This would reduce the number of IO cells in the ring, reduce die size, and improve the voltage drop.
Area IO flipchip
IO cells are placed in the core region as well as the ring.
A big opportunity to reduce the die size
Opportunity to reduce voltage drop
Many unknowns: noise in core; large blockages in core
Probably requires a totally new class of IO cell library to be developed
IO cells connect to the package via RDL routing, but less RDL routing is required.