CMOS Fundamentals
Q1. Why low power has become an important issue in the present day VLSI circuit realization?
Answer:
In deep submicron technology the power has bec : In deep submicron technology the power has become as one of the most important issue because of: Increasing transistor count; the number of transistors is getting doubled in every 18 months based on getting doubled in every 18 months based on Moore,s Moore,s Law Higher speed of operation;
the power dissipation is proportional to the clock frequency Greater device leakage currents; In nanometer technology the leakage component becomes a significant percentage of the total power and the leakage current increases at a faster rate than dynamic power in technology generations
Q2. How reliability of a VLSI circuit is related to its power dissipation dissipation?
Answer:
It has been observed that : It has been observed that every 10ºC rise in temperature ºC rise in temperature roughly doubles the failure roughly doubles the failure rate because various fa rate because various failure mechanism lure mechanism such as silicon interconnect fatigue, such as silicon interconnect fatigue, electromigrat electromigration diffusion, ion diffusion, junction diffusion and thermal runaway starts occurring as temperature increases.
Q3. How environment is affected by the power dissipation of VLSI circuits circuits?
Answer:
According to an estimate of the U.S. Environmental Protection Agency (EPA), 80% of the power consumption by office equipment are due to computing equipment and a large part from unused part from unused equipment.
Moreover, the power equipment. Moreover, the power is dissipated is dissipated mostly in the form of heat. The cooling techniques, such as AC transfers the heat to the environment.
Q4. Why leakage power dissipation has become an important issue in deep submicron technology in deep submicron technology?
Answer:
In deep submicron technology deep submicron technology the leakage component the leakage component becomes a significant percentage of the total power and the leakage current increases at a faster rate than dynamic power amic power in new technology technology generations.
That is why the leakage pow generations. That is why the leakage power has become an important issue.
Q5. Distinguish between energy and power dissipation of VLSI circuits. Which one is more important for portable systems systems?
Answer:
Power (P) is the power dissipation in Watts at : Power (P) is the power dissipation in Watts at different fferent instances of time. On the other has energy (E) refers to the energy consumed in Joule over a period of time (E = P*t).
Q6. What are the commonly used conducting layers used in IC fabrication?
Answer:
Fabrication involves fabrication of Fabrication involves fabrication of patterned laye atterned layers of the rs of the three conducting materials: metal, poly-silicon silicon and diffusion by using a series of photolithographic techniques and chemical processes involving oxidation of silicon, diffusion of impurities into the silicon and deposition and etching of aluminum or polysilicon polysilicon on the silicon to provide interconnectio on the silicon to provide interconnection.
Q7. Show the basic structure of a MOS transistor.
Answer:
The basic structure of a MOS transistor is given below. On a lightly doped substrate of silicon two islands of diffusion regions called as source and drain, of opposite polarity of that of the substrate, are created.
Between these two regions, a thin insulating layer of silicon dioxide is formed and on top of this a conducting material made of polysilicon or metal called gate is deposited.
Q8. What is the latch up problem that arises in bulk CMOS technology?
Answer:
The latch : The latch-up is an inherent problem in both n up is an inherent problem in both n-well as well a well as well as pwell based CMOS circuits.
The phenomenon is caused by the parasitic bipolar transistors formed in the bulk of silicon as shown in the figure for the n in the figure for the n-well process. well process. Latch-up can be defined as the formation of a low-impedance path between the power supply and formation of a low-impedance path between the power supply and ground rails through the parasitic ground rails through the parasitic npn and pnp bipolar transistors. bipolar transistors.
As shown the BJTs are cross as shown the BJTs are cross-coupled to form the st coupled to form the structure of a ructure of a silicon silicon-controlled controlled-rectifier (SCR) providing a short rectifier (SCR) providing a short-circuit path circuit path between the power rail and ground.
Leakage current through the parasitic resistors can cause one transistor to turn on, which in turn turns on the other transistor due to positive feedback and leading to heavy current flow and consequent device failure.
Q9. How the latch up problem can be overcome?
Answer:
There are several approaches to reduce the ten : There are several approaches to reduce the tendency of Latch of Latch-up. Some of the important techniques are up.
Some of the important techniques are mentioned below: Use guard ring around p Use guard ring around p- and/or n and/or n-well with frequent well with frequent contacts to the rings To reduce the gain product B1XB2Moving the n Moving the n-well and the n+ source/drain further well and the n+ source/drain further apart Buried n+ layer in well to reduce gain of Q1Higher substrate doping level to reduce R Higher substrate doping level to reduce R-sub Reduce R Reduce R-well by making low resistance contact to well by making low resistance contact to GND
Q10. Distinguish between the bulk CMOS technology with the SoI technology fabrications. technology fabrications.
Answer:
In bulk CMOS technology, a lightly doped p: In bulk CMOS technology, a lightly doped p-type or n-type substrate is used to fabricate MOS transis type substrate is used to fabricate MOS transistors. On the other hand, an insulator can be used as a substrate to fabricate MOS transistors
Q11. What are the benefits of SOI technology relative to conventional bulk CMOS technology?
Answer:
Benefits of SOI technology relative to convent : Benefits of SOI technology relative to conventional silicon al silicon (bulk CMOS):Lowers parasitic capacitance due to isolation from the bulk silicon, which improves power consumption and thus high speed performance.Reduced short channel effectsBetter sub Better sub-threshold slope. threshold slope.No Latch up due to BOX (buried oxide).Lower Threshold voltage.Reduction in junction depth leads to low leakage current.Higher Device density.
Q12. What are the basic assumptions of the fluid model?
Answer:
There are two basic assumptions as follows: : There are two basic assumptions as follows:
(a) Electrical charge is considered as fluid, which can move from one place to another depending on the difference in their level, of one from the other, just like a fluid.
(b) Electrical potentials can be mapped into the geometry of a container, in which the fluid can move around.
Q13. Explain the function of a MOS transistor in the Explain the function of a MOS transistor in the nonsaturation saturation mode using the fluid model mode using the fluid model.
Answer:
Gate voltage higher than the threshold voltage: Gate voltage higher than the threshold voltage and the drain d the drain voltage is slightly higher than source voltage.
In such a situation, as the drain voltage is increased the slope of the fluid flowing out increases indicating linear increase in the flow of current.
Q14. Explain the three modes of operation of a MOS transistors ransistors.
Answer:
The three modes are:
(a) Accumulation mode when Accumulation mode when Vgs is much less than is much less than Vt.
(b) Depletion Depletion mode when mode when Vgs is equal to is equal to Vt.
(c) Inversion Inversion mode when mode when Vgs is greater than is greater than Vt.
Q15. What are the three regions of operation of a MOS transistor?
Answer:
The three regions are:
Cut-off region: This is essentially the accumulation mode, where there is no effective flow of current between the source and drain.
Non-saturated region: This is the active, active, linear or week inversion region, where the drain current is dependent on both the gate and drain voltages.
Saturated region: This is the strong inversion region, where the drain current is independent of the drain drain current is independent of the drain-to-source voltage but urce voltage but depends on the gate voltage.
Q16. What is the threshold voltage of a MOS transistor? How it varies with the body bias?
Answer:
One of the parameters that characterizes the switching behavior of a MOS transistor is its threshold voltage Vt. This can be defined as the gate voltage at which a MOS transistor begins to conduct.
Q17. What is channel length modulation effect? How the voltage current characteristics are affected because of this effect?
Answer:
It is assumed that channel length remains constant as the drain voltage is increased appreciably beyond the on set of saturation. As a consequence, the drain current remains constant in the saturation region.
In practice, however the channel length shortens as the drain voltage is increased. For long channel lengths, say more than 5µm, this variation of length is relatively very small compared to the total length and is of little consequence.
However, as the device sizes are scaled down, the variation of length becomes more and more predominant and should be taken into consideration. As a consequence, the drain current increases with the increase in drain voltage even in the saturation region.
Q18. What is body effect? How does it influences the threshold voltage of a MOS transistor?
Answer:
All MOS transistors are usually fabricated on a common substrate and substrate (body) voltage of all devices is normally constant. However, as we shall see in subsequent chapters, when circuits are realized using a number of MOS devices, several devices are connected in series.
This results in different source potentials for different devices. It may be noted that the threshold voltage Vt is not constant with respect to the voltage difference between the substrate and the source of the MOS transistor.
This is known as the substrate-bias effect or body effect. Increasing the Vsb causes the channel to be depleted of charge carries and this leads to increase in the threshold voltage.
Q19. What is transconductance of a MOS transistor? Explain its role in the operation of the transistor.
Answer:
Trans-conductance is represented by the change in drain current for change in gate voltage for constant value of drain voltage. This parameter is somewhat similar to β, the current gain of bipolar junction transistors.
The following equation shows the dependence of on various parameters. As MOS transistors are voltage-controlled devices, this parameter plays an important role in identifying the efficiency of the MOS transistor.
Q20. How one nMOS and one pMOS transistor are combined to behave like an ideal switch.
Answer:
To overcome the limitation of either of the transistors, one pMOS and one nMOS transistor can be connected in parallel with complementary inputs at their gates. In this case we can get both LOW and HIGH levels of good quality at the output.
The low level passes through the nMOS switch and HIGH level passes through the pMOS switch without any degradation as shown in the figure
Q21. The input of a lightly loaded transmission gate is slowly changes from HIGH level to LOW level. How the currents through the two transistors vary?
Answer:
Another situation is the operation of the transmission gate when the output is lightly loaded (smaller load capacitance).
In this case, the output closely follows the input. In this case the transistors operate in three regions depending on the input voltage as follows:
Region I: nMOS non-saturated, pMOS cut-OFF.
Region II: nMOS non-saturated, pMOS non-saturated.
Region III: nMOS cut off, pMOS non-saturated.
Q22. How its ON-resistance of a transmission gate changes as the input varies from 0 V to Vdd, when the output has a light capacitive load.
Answer:
The variation of ON resistance is shown in the figure. The parallel resistance remains more or less constant.
Q23. Draw the ideal characteristics of a CMOS inverter and compare it with the actual characteristics.
Answer:
The ideal and actual characteristics are given below. In the ideal characteristics, the output voltage is Vdd for input voltage from o to Vdd/ and 0 for input voltage from Vdd/ to Vdd. This is not true in case of the actual characteristics as shown below.
Q24. Compare the characteristics of the different types of MOS inverters in terms of noise margin and power dissipation.
Answer:
Various characteristic parameters are compared in the following table:
Q25. What is the inversion voltage of an inverter? Find out the inversion voltage of a CMOS inverter.
Answer:
The inversion voltage Vinv is defined as the voltage at which the output voltage Vo is equal to the input voltage Vin. For a CMOS inverter it can be expressed in terms of the threshold voltages of the MOS transistors and other parameters.
Q26. How the noise margin is affected by voltage scaling?
Answer:
As the supply voltage is reduced, the margin also decreases as shown in the figure.
Q27. What is the lower limit of supply voltage of a CMOS inverter. What happens if the supply voltage is further reduced?
Answer:
The lower limit of the supply voltage depends on the sum of the threshold voltages of the nMOS and the pMOS transistors. Vdd = Vtn +|Vtp|. As the supply voltage is reduced further, it leads to hysteresis in the transfer characteristic.
Q28. What is sheet resistance? Find out the expression of the resistance of rectangular sheet in terms of sheet resistance.
Answer:
The sheet resistance is defined as the resistance per unit area of a sheet of material. Consider a rectangular sheet of material with Resistivity = , Width = W, Thickness = t and Length = L. Then, the resistance between the two ends is
Q.29 Find out the capacitance of a MOS capacitor.
Answer:
The capacitance of a parallel plate capacitor is given by
Q30. Explain the basic concept of super buffer.
Answer:
There are situations when a large load capacitance such as, long buffers, off-chip capacitive load, or I/O buffer are to be driven by a gate. In such cases, the delay can be very high if driven by a standard gate. Limitations of driving by a simple nMOS inverter is the asymmetric drive capability of pull-up and pull-down devices (ratioed logic).
Moreover, when the pull-down transistor is ON, the pull-up transistor also remains ON. So, the pull-down transistor should also sink the current of the pull-up device. Although this limitation is overcome in CMOS circuits, there is asymmetry in drive capability of pull-up and pull-down devices having the same minimum size
Q.31 Draw the schematic diagram of an inverting and non-inverting super-buffers and explain its operation.
Answer:
The schematic diagrams of the super buffers are given below.
The average of the saturation currents for Vds = 5V and linear current for Vds = .5V is approximately 4.4 βpu for the standard inverter.
On the other hand the, for the super-buffer, the average current is 19.06 βpu, which is 4 times that of standard inverter. Thus, the pull-up device is capable of sourcing about four times the current of the standard nMOS inverter.
Q32. Give the schematic diagram of a Bi-CMOS inverter. Explain its operation. Compare the switching characteristics of a BiCMOS inverter with respect to that for static CMOS for different fan out conditions.
Answer:
The schematic diagram of a BiCMOS inverter is given below. Higher current drive capability of bipolar NPN transistors is used in realizing bi-CMOS inverters. The delays of CMOS and BiCMOS inverters are compared for different fan-outs.
It may be noted that for fan-out of 1 or CMOS provides smaller delay compared to BiCMOS. However, as fan-out increases further, BiCMOS performs better and better.
Q33. How the transfer characteristic of a CMOS NAND gate is affected with increase in fan-in?
Answer:
Transfer characteristic does not remain symmetric with increase in fan-in of the NAND gate. The inversion voltage moves towards right with the increase in fan-in.
Q34. How the transfer characteristic of a CMOS NOR gate is affected with increase in fan-in?
Answer:
In case of NOR gate the transfer characteristic also does not remain symmetric and the inversion voltage moves towards left with the increase in fan-in.
Physical Design Interview Questions with Answer
Q35 How switching characteristic of a CMOS NAND gate is affected with increase in fan-in?
Answer:
When the load capacitance is relatively large, the fall time increases linearly with the increase in fan-in and the rise time is not affected much.
Q36. How switching characteristic of a CMOS NOR gate is affected with increase in fan-in?
Answer:
When the load capacitance is relatively large, the rise time increases linearly with the increase in fan-in and the fall time is not affected much.
For the same area, NAND gates are superior to NOR gates in switching characteristics because of higher mobility of electrons compared holes. For the same delay, NAND gates require smaller area than NOR gates
Q37. How noise margin of a CMOS NAND/NOR gate is affected with increase in fan-in?
Answer:
Because of the change in the inversion voltage, the noise margin is affected with the increase in fan-in. For equal fan-in, noise margin is better for NAND gates compared to NOR gates.
We may conclude that for equal area design NAND gates are faster and better alternative to NOR gates
Q38. For a complex/compound CMOS logic gate, how do you realize the pull-up and the pull-down networks?
Answer:
A CMOS logic gate consists of a nMOS pull-down network and a pMOS pull-up network. The nMOS network is connected between the output and the ground, whereas the pull-up network is connected between the output and the power supply.
The nMOS network corresponds to the complement of the function either in sum-of-product or product-of-sum forms and the pMOS network is dual of the nMOS network .
Q.39 Give the two possible topologies AND-OR-INVERT AND-OR- INVERT (AOI) and OR-AND-INVERT (OAI) to realize CMOS logic gate. Explain with an example.
Answer:
The AND-OR-INVERT network corresponds to the realization of the nMOS network in sum-of-product form. Where as the OR- AND-INVERT network corresponds to the realization of the nMOS network in product-of-sum form. In both the cases, the pMOS network is dual of the nMOS network .