Q42. In what way relay logic circuits differ from pass transistor logic circuits? Why the output of a pass transistor circuit is not used as a control signal for the next stage?
Answer:
Logic functions can be realized using pass transistors in a manner similar to relay contact networks. However, there are some basic differences as mentioned below:
(a)In relay logic, output is considered to be ‘1’ when there is some voltage passing through the relay logic. Absence of voltage is considered to be ‘0’.
On the other hand, is case of pass transistor logic it is essential to provide both charging and discharging path for the output load capacitance.
(b)There is no voltage drop in the relay logic, but there is some voltage drop across the pass transistor network.
(c)Pass transistor logic is faster than relay logic.
Q43. What are the advantages and limitations of pass transistor logic circuits? How the limitations are overcome?
Answer:
Pass transistor realization is ratioless, i.e. there is no need to have L:W ration in the realization. All the transistors can be of minimum dimension.
Lower area due to smaller number of transistors in pass transistor realization compared to static CMOS realization. Pass transistor realization also has lesser power dissipation because there is no static power and short-circuit power dissipation in pass transistor circuits.
The limitations are (a) Higher delay in long chain of pass transistors (b) Multi-threshold Voltage drop (Vout = Vdd – Vtn) (c) Complementary control signals and (d) Possibility of sneak path because of the presence of path to Vdd and GND.
Q44. Why is it necessary to insert a buffer after not more than four pass transistors in cascade?
Answer:
When a signal is steered through several stages of pass transistors, the delay can be considerable. For n stages of pass transistors, the delay is given by the relationship.
To overcome the problem of long delay, buffers should be inserted after every three or four pass transistor stages.
Q45. Why is it necessary to have swing restoration logic in pass transistor logic circuits? Explain its operation.
Answer:
In order to avoid the voltage drop at the output (Vout = Vdd – Vtn) , it is necessary to use additional hardware known swing restoration logic at the gate output. At the output of the swing restoration logic there is rail to rail voltage swing.
The swing restoration can be done using a pMOS transistor with its gate connected to GND.
Q46. What is the ‘sneak path’ problem of pass transistor logic circuits? How sneak path is avoided in Universal Logic Module (ULM) based realization of pass transistor network. Illustrate with an example.
Answer:
As shown in the figure, the output is connected to both ‘1’ (Vdd) and ‘0’(GND). The output attains some intermediate Value between Vdd and GND. The MUX based realization allows connection of the output to only one input, which can be either 0 or 1.
Multiplexer realization of Is shown in the figure.
Q47. Explain the basic operation of a 2-phase dynam phase dynamic circuit? ic circuit?
Answer:
The operation of the circuit can be explained : The operation of the circuit can be explained using precharge precharge logic in which the output is logic in which the output is precharged precharged to HIGH level during to HIGH level during φ2 clock and the clock and the output is evaluated during output is evaluated during φ1 clock 1 clock.
Q48. How phase clocks can be generated using inverters?
Answer:
As shown below, two phase clock can generated using inverters. The timing diagram is given in the next slide.
Timing diagram of the two-phase clock generated from a single-phase clock.
Q49. What makes dynamic CMOS circuits faster than static CMOS circuits?
Answer:
As MOS dynamic circuits require lesser number of transistors and lesser capacitance is to be driven by it. This makes MOS dynamic circuits faster.
Q50. Compare the sources of power dissipation between static CMOS and dynamic CMOS circuits?
Answer:
In both the cases there is switching power and leakage power dissipations. However, the short circuit and glitching power dissipations, which are present in static CMOS circuits, are not present in dynamic CMOS circuits.
Q51. What is charge leakage problem of dynamic CMOS circuits? How is it overcome?
Answer:
The source-drain diffusions form parasitic diodes with the substrate. There is reverse bias leakage current .The current is in the range 0.1nA to 0.5nA per device at room temperature and the current doubles for every 10°C increase in temperature .
This leads to slow but steady discharge of the charge on the capacitor, which represent information. This needs to be compensated by refreshing the charge at regular interval.
Q52. Explain the clock skew problem of dynamic CMOS circuits?
Answer:
Clock skew problem arises because of delay due to resistance and parasitic capacitances associated with the wire that carry the clock pulse and this delay is approximately proportional to the square of the length of the wire.
When the clock signal reaches a later stage before its preceding stage, the precharge phase of the preceding stage overlaps with the evaluation phase of the later stage, which may lead to premature discharge of the load capacitor and incorrect output during evaluation phase
Q53. How clock skew problem is overcome in in domino CMOS circuits?
Answer:
In domino CMOS circuits the problem is overcome by adding an inverter as shown in the diagram. It consists of two distinct components: The first component is a conventional dynamic CMOS gate and the second component is a static inverting CMOS buffer.
During precharge phase, the output of the dynamic gate is high, but the output of the inverter is LOW.As a consequence, it cannot drive an nMOS transistor ON. So, the clock skew problem is overcome.
Q54. How clock skew problem is overcome in in NORA CMOS circuits?
Answer:
The problem can be overcome using NORA logic, nMOS and pMOS transistor networks are alternatively used.
The output of an nMOS block is HIGH during precharge, which cannot turn a pMOS transistor ON. Similarly, the output of an pMOS block is LOW during precharge, which cannot turn a nMOS transistor ON.
Q55. Distinguish between Mealy and Moore machines.
Answer:
In a Mealy machine the outputs are dependent on the inputs and present state. The Output transition function is represented by Z = λ(S,X).
Where as in a Moore machine the outputs are dependent only on present state. The output transition function is represented by Z = λ((S)
Q56. List various sources of leakage currents.
Answer:
Various sources of leakage currents are listed : Various sources of leakage currents are listed below:
- I1= Reverse = Reverse-bias p-n junction diode leakage current n junction diode leakage current
- I2 = Band-to-band tunneling current band tunneling current
- I = Subthreshold leakage current
- I3 = Subthreshold leakage current
- I4 = Gate Oxide tunneling current
- I5 = Gate current due to hot Gate current due to hot-carrier injection carrier injection
- I6 = Channel punch Channel punch-through through
- I7 = Gate induced drain Gate induced drain-leakage current leakage current
Q57. Why leakage power is an important issue in deep submicron technology?
Answer:
In deep submicron technology, the leakage component is a significant % of total power as shown in the diagram. Moreover, the leakage current is increasing at a faster rate than dynamic power.
As a consequence, it has become an important issue in DSM.
Q58. What is band-to-band tunneling current?
Answer:
When both n regions and p regions are heavily doped, a high electric field across a reverse biased p high electric field across a reverse biased p-n junction causes nction causes significant current to flow through the junction due to tunneling of electrons from the valence bond of the p of electrons from the valence bond of the p-region to the to the conduction band of n conduction band of n-region. This is known as band region. This is known as band-to-band tunneling.
Q59. What is body effect?
Answer:
As a negative voltage is applied to the substrate with respect to the source, the well respect to the source, the well-to-source junct source junction the device is ion the device is reverse biased and bulk depletion region is widened.
This leads to increase the threshold voltage. This effect is known as body effect.
Q60. What is subthreshold leakage current? Briefly discuss various mechanisms responsible for this leakage current?
Answer:
The subthreshold subthreshold leakage current in CMOS circuits is due leakage current in CMOS circuits is due to carrier diffusion between the source and the drain regions of the transistor in weak inversion, when the gate voltage is below Vt.
The behavior of an MOS transistor in the subthreshold operating region is similar to a bipolar device, and the region is similar to a bipolar device, and the subthreshold hreshold current exhibits an exponential dependence on the gate voltage.
The amount of the amount of the subthreshold current may become significant current may become significant when the gate when the gate-to-source voltage is smaller than source voltage is smaller than, but very close , but very close to the threshold voltage of the device.
Q61. Explain the basic concepts of supply voltage scaling.
Answer:
Power dissipation is proportional the square of the supply voltage. So, a factor of two reduction in supply voltage yields a factor of four decrease in energy. But, as the supply voltage is reduced, delay increases as shown in the diagram. So, the challenge is to scale down the supply voltage without compromise in performance.
Q62. As you move to a new process technology with a scaling factor S = 1.4, how the drain current, power dissipation, power density, delay and energy requirement changes for the constant field scaling?
Answer:
Drain current reduces by a factor of S. Although po ough power dissipation decreases by a factor of S2 , the power density remains the same. The delay decreases by a factor of S and the energy decreases by a factor of S3 .
Q63. Distinguish between constant field and constant voltage feature size scaling? Compare their advantages and disadvantages.
Answer:
In this approach the magnitude of all the inte : In this approach the magnitude of all the internal electric fields l electric fields within the device are preserved, while the dimensions are scaled down by a factor of S.
This requires that all potentials must be scaled down by the same factor. Accordingly, supply as well as threshold voltages are scaled down proportionately.
But, in constant constant-voltage scaling, all the device dimension voltage scaling, all the device dimensions are scal s are scaled down by a factor of S just like constant down by a factor of S just like constant-voltage s voltage scaling, supply caling, supply voltage and threshold voltages are not scaled.
Q64. Compare Compare the constant constant field and constant constant voltage voltage scaling scaling approaches approaches in terms of area, delay, energy and power density density parameters parameters.
Answer:
Q65. Explain how parallelism can be used to achieve low power instead of high performance in realizing digital circuits.
Answer:
Traditionally, parallelism is used to improve performance at the expense of larger power dissipation. But, instead of trying to improve performance, the power dissipation can be reduced by scaling down the supply voltage such that the performance remains unaltered.
Q66. Explain how multicore architecture provides low power compared to the single core architecture of the same performance.
Answer:
The idea behind the parallelism for low-power can be extended to multi-core architecture. The clock frequency can be reduced with commensurate scaling of the supply voltage as the number of cores is increased from one to more than one while maintaining the same throughput.
Q67. Explain the basic concept of multi level voltage scaling.
Answer:
This is an extension of SVS where two or few fixed voltage domains are used in different parts of a circuit,. As we know, high Vdd gates have less delay, but higher dynamic and st gates have less delay, but higher dynamic and static power dissipation and low power dissipation and low Vdd gates have larger delay but gates have larger delay but lesser power dissipation.
Voltage islands can be generated at different levels of granularity, such as macro level and standard cell level.
The slack of the off-cell level. The slack of the off-critical path can critical path can be utilized for be utilized for allocation of macro modules of low allocation of macro modules of low-Vdd to off-critical critical-path macro modules. Total power dissipation can be reduced without degrading the overall circuit performance.
Q68. What is the impact of multiple supply voltages on the distribution of path delays of a circuit with respect to that for single supply voltage?
Answer:
Path delay for different paths in a circuit for single supply voltage is shown. The graph of a Gaussian is a characteristic symmetric “bell curve” shape that quickly falls off towards plus/minus infinity plus/minus infinity.
However, when multiple supply voltages are used, the path delay distribution is not Gaussian because modules having smaller delays are assigned with smaller supply voltage and their delay increases.
Q69. List and explain the important issues in the context of multiple supply voltage scaling?
Answer:
Important issues in the context of MVS are listed below:
- Voltage Scaling Interfaces
- Converter Placement
- Floor planning, Routing and Placement
- Multiple Supply Voltages
- Static Timing Analysis
- Power up and Power down Sequencing
- Clock distribution
Q70. What problem arises when a signal passes from low voltage domain to high voltage domain? How this problem is overcome?
Answer:
A high-level output from the low level output from the low-Vdd domain has output domain has output VddL, which may turn on both , which may turn on both nMOS and pMOS transistors of the transistors of the high-Vdd domain inverter resulting in short circuit between VddH to GND. A level converter needs to be inserted to avoid this static power consumption
Q71. Explain the design decision for the placement of converters in the voltage scaling interfaces.
Answer:
One important design decision in the voltage : One important design decision in the voltage scaling interfaces is the placement of converters . As the high the high-to-low level converters use low low level converters use low-Vdd voltage voltage rail, it is a appropriate to place them in the receiving or destination domain.
It is also recommended to place the low place the low-to-high level converters in the r high level converters in the receiving eceiving domain. As the low domain. As the low-to-high level converters req high level converters require both low and high both low and high-Vdd supply rails, at least one of the supply rails, at least one of the supply rails needs to be routed from one domain to the other.
Q72. What problem arises when a signal passes from low voltage domain to high voltage domain? How this problem is overcome?
Answer:
A high-level output from the low level output from the low-Vdd domain has output domain has output VddL, which may turn on both , which may turn on both nMOS and pMOS transistors of the transistors of the high-Vdd domain inverter resulting in short circuit between VddH to GND. A level converter needs to be inserted to avoid this static power consumption