There are some guidelines that need to be followed while placing macros to avoid congestion and other design problems from occurring at the later stages of the design.
Macros and all other logics will be sitting outside the die area, once the core and die gets created.
What are macros?
Macros are larger functional blocks like the IC’s memories (SRAM, ROM), analog devices (DAC, ADC), clock macros (PLLs), or interface macros. These macros are typically provided by third-party IP (Intellectual Property) vendors or developed in-house by the design team. Some of the qualities of a macro are:
- They consume a larger area.
- They are power-hungry devices i.e. they consume huge power.
- They are placed at the boundary of the core area.
After executing shape_blocks command, tool will do a rough placement of macros.
Macro Placement guidelines:
What guidelines should I follow when placing hard macros in the floorplan?
This solution provides designers performing physical design (Place & Route) with tips and guidelines to create an initial floorplan. These guidelines will help you maximize the space available for standard cell placement, avoid routing congestion problems, and achieve the power supply routing requirements.
This solution focuses on two main areas to help you achieve high-density designs:
- Macro Placement
- Row Generation
These tips range from simple guidelines to more advanced ones that may or may not apply to your design. For your design, you also have to take into account specific conditions and constraints such as:
- Timing
- Clock
- Power
- IP specific restriction
- DFT test
- Place macros around chip periphery
If you do not have a rationale to place the macro inside the core area, place macros around the chip periphery. Placing a macro inside the core can invite serious consequences during routing due to a lot of detour routing.
This is because macros are equal to a large obstacle for routing. Also, placing the hard macros around the core-periphery makes it easier to supply power to these macros, and reduces the chance of IR drop problems for macros consuming high amounts of power.
2. Consider connections to fixed cells when placing macros
When you decide the macro position, you have to pay attention to connections to fixed elements such as I/O and pre-placed macros. Place macros near the corresponding associate fixed elements. Check connections by displaying flight lines in the GUI.
3. Orient macros to minimize the distance between pins
When you decide the orientation of macros, you also have to take into account the positions of the pins and the respective connections.
4. Reserve enough room around macros
For regular net routing and power grid, you have to reserve enough routing space around macros. In this case, estimating routing resources with precision is very important.
Use the congestion map from trialRoute to identify hotspots between macros and adjust the placement as needed.
5. Reduce open fields as much as possible
Except for reserved routing resources, remove dead space to increase the area for random logic.
Choosing a different aspect ratio (if that option is available) can eliminate open fields.
6. Reserve space for power grid
The number of required power routes can change based on the power consumption.
You have to estimate the power consumption and reserve enough room for the power grid. If you underestimate the space required for power routing, you can encounter routing problems.
Note: At least one pair of metal layer tracks must be between two macros. This pair of tracks will be used as Vss and Vdd in the power planning stage. If the standard cell is present between the macros and if the metal layers between the macros are not, then this will lead to an IR drop.