Physical Design Flow in VLSI

PD Flow in VLSI

Synthesis flow

• In this phase, the high-level RTL code is converted into an
  optimized gate-level representation using a standard cell library
  and design constraints.
• Logic equivalence checks confirm that no logical modifications
  occur during synthesis.
• Reports on timing, power, and area are produced during this step.

The high-level RTL code is transformed into an optimized gate-level
representation
Elaborate output
GTECH File

• The GTECH file provides a detailed netlist representation.
• It is an intermediate, equation-based design format that is
  technology-independent.
• This file acts as a middle step after the elaboration phase.
• It includes details about the design’s structure, connectivity, and
  generic parameters.
• Although not easily readable by humans, it is utilized internally by
  the synthesis tool for further optimization and technology mapping
  processes.
• GTECH files are typically saved with a .db extension

Floor Planning in Physical Design
Floor planning plays a crucial role in the physical design phase of chip development. It sets up the fundamental layout of the chip and decides where major components will be positioned.

• Die Size Estimation: Calculate the core’s width and height to estimate the total die size.
• Aspect Ratio: Establish the proportion between the chip’s width and height.
• Core Utilization: Determine the space used by standard cells,
  input/output (IO) pins, macros, and other elements.
  This approach ensures an organized and efficient layout, which is essential for achieving optimal performance and manufacturability of the chip.

At the beginning the cells are not placed inside the core

Cell and Pin Placement:

Power Distribution Strategy

• Power Distribution Strategy involves planning how to efficiently route power from the power pads to the various standard cells and macros within the design.
• The goal is to achieve a consistent power supply with minimal voltage drops.
• Power Rings: These are complete rings of power (VDD, GND) that encircle the die’s perimeter, individual hard macros, or higher-level hierarchical blocks. They are implemented using upper metal
  layers to ensure comprehensive power delivery.
• Power Stripes (Straps): These are horizontal and vertical metal strips that extend across the chip, distributing VDD and VSS from the power rings throughout the chip. They form an array across the
  die sections.

• Power Rails: These connect the standard cells with the power straps. Typically, they use a low metal layer, often metal 1, as standard cells are usually placed on this layer.
• Electromigration (EM) Considerations: EM refers to the migration of metal atoms due to high current densities in metal traces. Effective power planning is crucial to mitigate EM-related issues,
  such as the formation of voids or hillocks in the metal layers, which could adversely affect the chip’s performance.

Power ring placement, Mesh Creation, Power rail placement
Power rails are essential for evenly distributing power to all parts of the
chip, typically arranged on the metal layers. The goal of power planning,
including creating power rails, is to adhere to the IR drop budget. IR
drop refers to the voltage decrease that happens in power supply
networks.

• Ideal power supply availability is assumed in IC design. In practice, localized voltage drops occur within the power grid due to increasing current density on the die and narrower metal
  line widths, which raise power grid resistance.
• This leads to a reduction in power supply voltage at the cells or transistors.
• Consequently, the operating voltage of the chip decreases, causing timing and functional failures.

Placement
Optimizing Design Quality through Effective Placement in Synopsys EDA Tools

• Pre-Placement: Before initiating the actual placement of the standard cells in the synthesized netlist, various physical-only cells such as end-cap cells, well-tap cells, IO buffers, antenna diodes, and spare
  cells are positioned.
• Initial Placement / Global Placement / Coarse Placement: Following the pre-placement stage, the placement of standard cells begins. The tool aims to position the standard cells to achieve minimal congestion and optimal timing. After configuring these placement settings, the placement command is executed.
• Legalization: Post-initial placement, the cells are legalized. This involves adjusting the placement of cells slightly to ensure they align with the placement sites on the rows.
• High Fanout Net Synthesis (HFNS): In this process, high fanout nets are segmented into smaller, more manageable nets.
• Iteration for Congestion, Timing, DRC, and Power Optimization: The tool performs multiple iterations to optimize the design for improved timing, reduced congestion, and enhanced power efficiency.
• Multi-bit Flop Conversion: Single-bit flip-flops are replaced with multi-bit flip-flops to save area and power.
• Timing Optimization Iterations: The tool conducts several iterations to meet the design’s timing requirements.
• Scan-Chain Reorder: The scan chains are reordered to reduce the wire length.
• Tie Cell Insertion: Tie cells are inserted to provide a known logic value to the inputs of cells.
• Save Design: Finally, the design is saved after completing the placement and optimization stages.

The place_opt command is integral to the physical design flow of VLSI ASIC
design, specifically during the placement and optimization phase. Here is a detailed
overview of its sub-commands:

place_opt command in placement:

1. Initial Coarse Placement (initial_place):

• Executes placement considering buffering and timing constraints.
• Optimizes the scan chain for better performance.

1. HFN Buffering (initial_drc):

• Eliminates unnecessary buffer trees.
• Synthesizes high fanout nets and fixes logic design rule violations.

1. Initial Optimization (initial_opto):

• Conducts preliminary timing optimization to enhance performance.

1. Final Placement (final_place):

• Carries out incremental and final placement driven by timing and
  congestion considerations.
• Includes global routing and scan chain optimization.

1. Final Optimization (final_opto):

• Executes comprehensive final optimization to improve the design.
• Legalizes the design ensuring all design rules are met.
  Each sub-command focuses on specific aspects of the design, progressively
  refining it from initial placement to a fully optimized state.

Clock Tree Synthesis (CTS)

Clock Tree Synthesis (CTS) is a vital phase in the physical design process of VLSI ASIC design. It entails the automated placement of buffers and inverters along the clock routes within the ASIC layout to
equalize the clock delay to all clock inputs.
Objectives:

• Primary Aim: The principal aim of CTS is to ensure that all clocked components in the design activate simultaneously.
• Methodology: This synchronization is attained by equalizing the clock paths, which minimizes insertion delay and balances the clock skew.
  Pre-check design:

Set Clock Tree Target Skew: This command establishes a target skew of 0.5 for all clocks within the design. Skew refers to the variance in clock arrival times between any two sequential elements. By setting a target skew, you aim to achieve uniform clock arrival times across the design, which assists in meeting setup and
hold time requirements, ultimately enhancing the design’s performance.

Set Clock Tree Target Latency: This command sets a target latency for all clocks in the design. Latency is the delay from the clock source to the sequential elements.

By establishing a target latency, you aim to control the delay within the clock network, which can help reduce power consumption and improve the overall timing of the design.

These commands guide the Clock Tree Synthesis (CTS) process to meet specific design objectives, allowing you to balance power, performance, and area based on your design requirements.

It’s important to remember that these are target values; actual results may vary depending on the design’s complexity and the synthesis tool’s capabilities. Always verify the results after CTS to ensure the design goals are achieved.

Clock Optimization Commands

• clock_opt -from build_clock -to build_clock: This command enhances the clock network
  during the build_clock phase. It is primarily used to minimize skew and enhance the
  quality of the clock tree constructed in this stage.
• clock_opt -from build_clock -to route_clock: This command fine-tunes the clock network
  from the build_clock phase to the route_clock phase. It provides further refinement to the
  clock tree after the initial construction, leveraging additional placement information.
• clock_opt -from route_clock -to final_opto: This command adjusts the clock network
  from the route_clock phase to the final optimization phase. It is used to make final
  refinements to the clock tree post-routing, ensuring the design meets timing, power, and
  area objectives.

Quality of Results (QoR) in Clock Tree Synthesis (CTS)
In Clock Tree Synthesis (CTS), Quality of Results (QoR) signifies the effectiveness of the
synthesized clock tree in meeting design objectives. These objectives usually encompass:

• Timing: The clock tree must satisfy setup and hold time constraints. Key aspects influencing this include clock skew and clock latency.
• Power: Reducing power consumption in the clock tree is crucial. This is determined by factors such as the quantity and types of buffers deployed.
• Area: Minimizing the physical space taken up by the clock tree is essential. The area is
  affected by the number and types of buffers used.
• Reliability: The clock tree should be resilient to variations in process, voltage, and
  temperature (PVT variations).
  The QoR for CTS is assessed using several metrics, including total wire length, maximum and
  total skew, total buffer area, and overall power consumption. The importance of these metrics
  can vary based on the specific design priorities.
• For instance, in low-power designs, reducing power consumption might be the primary concern, whereas, in high-performance designs, achieving timing requirements could be the main focus.

The Routing Stage in ASIC Physical Design
The routing stage, also referred to as wire routing, is one of the concluding steps in the ASIC physical design flow. This stage follows Clock Tree Synthesis (CTS) and optimization, where the logic gates are positioned on the chip.

The main goal of the routing stage is to establish physical paths for electrical signals to travel between these gates.

• Global Routing: This initial step involves creating a rough path for each net (a group of pins that must be electrically connected). The process considers the chip as a grid of larger sections, determining the optimal path for each net to minimize total wirelength and avoid congestion.
• Detailed Routing: Following global routing, detailed routing is executed.
  This step defines the exact paths of the wires at the transistor level. The router must ensure that the wires adhere to design rules, such as minimum spacing and width requirements. Additionally, it must account for parasitic capacitance and resistance, which can affect signal integrity and timing.
• Post-Routing Optimization: After the initial routing, post-routing optimization is performed to enhance the design’s quality. This may involve adjusting wire widths to reduce resistance, adding buffers to improve signal integrity, or rerouting certain nets to reduce congestion and improve timing.
  The outcome of the routing stage is a fully placed and routed design, ready for extraction and verification. This stage is crucial as it directly influences the final chip’s performance, power consumption, and area. It is a complex task requiring advanced algorithms and tools to manage the various trade-offs and constraints.

The connect_pg_net -automatic command is utilized in the VLSI (Very Large Scale Integration) physical design process to automatically link power and ground nets within the design. When encountering issues related to insufficient spacing on a metal layer, such as Metal 1, it is often a result of manual or semi-automatic power/ground routing that does not fully adhere to the design rules specific to the technology node in use.

These rules specify the minimum spacing required between metal tracks. By employing the connect_pg_net -automatic command, the tool assumes responsibility for connecting power and ground nets while ensuring compliance with the design rules of the technology node.

This includes adhering to rules regarding spacing, width, and via densities, among other factors.
Consequently, issues related to insufficient spacing can be resolved, as the tool guarantees adherence to all relevant rules during the connection of power and ground nets.