1.what are half cycle paths? In half cycle path which one is critical? Setup or hold?
A path which requires only half cycle to capture the data. It is formed when data is
launched on positive edge of the clock and captured on negative edge of the clock or when
data gets launched on negative edge of the clock and gets captured on positive edge of the
clock.
In such paths, setup check become tighter as setup gets only half cycle while hold
constraint is relaxed by half cycle.
The falling edge occurs at 5ns and the rising edge occurs at 10ns. Thus, the data gets only a
half-cycle, which is 5ns, to propagate to the capture flip-flop.
While the data path gets only half- cycle for setup check, an extra half-cycle is available for the hold timing check.
The hold check always occurs one cycle prior to the capture edge. Since the capture edge
occurs at 10ns, the previous capture edge is at 0ns, and hence the hold gets checked at 0ns.
This effectively adds a half-cycle margin for hold checking and thus results in a large positive
slack on hold.
2. If you are facing congestion globally, what is the reason for that?
a) The reason maybe bad floorplan.
3. After cts optimization how you will fix hold?
a) By skewing the clock path, we will fix the timing violations. Hold can be fixed by
pushing (adding buffers) launch path and pulling (removing buffers) the capture path.
4. what stage filler cells can be added?
a) After post route optimization we will add buffers in the design.
5. What is ICG? What is the advantage of ICG?
a) Clock gating is a very common technique to save power by stopping the clock to a module
when the module is not operating. The advantage of ICG cell is , it reduces dynamic power
consumption.
6. What you will fix first if there is setup , hold and DRV’s?
a) First we have to fix DRV’s and then setup and then hold.
7. In netlist we didn’t find pg pin information then where will you find this?
In def file we have information of special nets (VDD , VSS).
8. What issues you faced in placement?
a) Congestion and timing violations
9. Did you get congestion between macro channel?
No, I didn’t get congestion between macro channel. Some standard cells are placed but
congestion didn’t occur.
If I get congestion between macro channel, then I will solve that congestion by applying hard blockage.
10. Which one is important skew or latency?
a) Latency is important than skew. If timing is met for both scenarios then which one
you will choose?
skew =50ps, latency =200ps
skew =70ps , latency = 150ps
we will choose less latency i.e skew = 70 and latency = 150ps . because more latency ,
more buffers will be added due to this power consumption increases, area increases. So ,
to reduce power consumption and area we will give more importance to the latency.
11. What is the difference between soft , hard and partial blockages?
a) soft blockage: It won’t allow std cells to place in that area during global
placement. But it allows buffers and inverters during optimization.
Hard blockage: It won’t allow std cells to place in that area during global
placement and optimization also.
Partial blockage: It allow some percentage of std cells in that area.
12. How will you apply derates for setup and hold?
For setup: early derates are applied to capture path and late derates are applied to
launch path.
For hold: early derates are applied to launch path and late derates are
applied to capture path.
13. What is transition and what parameters affects it?
a) The time taken by the signal to switch from one state to another state is called
transition time.
Rise transition: The time taken by the signal to switch from 10% of its input to 90% of its output is called rise transition.
Fall transition: The time taken by the signal to switch from 90% of its input to 10% of its output is called fall transition.
The parameter effects transition are: High fanout, long nets.
14. How to fix transition?
Add buffer if net delay dominates buffer delay
Upsize the driver
15. How to analyze timing reports?
- First look at starting and ending points is both are triggered by the same clock or different clock. if it is different clock then check both clocks are synchronous or asynchronous.
- Then see the slack value. if slack is violating more than 1ns, then analyze why it is violating that much. This violation occurs maybe due to constraint missing like multi cycle path or half cycle path.
- If slack is less, then seeing the report for which cell is taking more delay. And analyze why this cell taking this much delay i.e.) observe input trans and output cap of the cell.
- Find the no.of violating paths, if more paths violating with single start point and multiple endpoints then trace out diverging point from starting point. And do changes before diverging point.
16. What are NDR’s?
a) NDR’s (non-default routing rule) are used on clock nets. because clock nets are high switching activity nets, so they effected more on cross talk and EM issues. In my design we used 2w2s. double width to avoid EM violation and double space to avoid cross talk violation
17. Why are clock buffers not used in data path?
a) Because the size of clock buffer is large compared to normal buffer, it consumes more power and more area.
18. What is DRC and LVS?
a) DRC: DRC is design rule violations. In DRC it checks the design is meting DRC rules given by foundry or not.
LVS: LVS means Layout versus schematic. It is a method of verifying that the layout of the design is functionally equivalent to the schematic of the design.
19. Opens and shorts they are LVS issues or DRC issues?
a) opens and shorts are related to LVS issues.
20. DRC is passing and LVS is failing, does this scenario exists?
a) Yes
21. LVS is passing, and DRC is failing, does this scenario exists?
a) Yes.
22. What is cross talk noise?
a) It is undesired change in the output values of victim due to switching in the input of
aggressor. If one net is switching and other is at a constant value, the switching net may
cause voltage spikes on other net. This is called as cross talk noise.
Cross talk noise is evolving as a key source in degrading performance and reliability of high-speed integrated circuits.
23. What is cross talk delay?
a) When there is some delay in output transition of victim due to input transition of
aggressor, it is called as cross talk delay.
It occurs when some transition is happening in both the nets. Cross talk delay depends on the switching direction of the aggressor and victim nets too.
If input transitions occur in same direction, then output transition of victim becomes faster and if input transitions occur in opposite directions, then output transition of victim becomes slower and delay is more which may violate setup time.
24. What are all the delay for given path consisting of two flops?
a) The delays in the data path are launch latency, Tcq (propagation delay of the flip flop), combinational delay
The delays in the clock path are capture latency, Tsetup (library setup time of a flop), Thold (library hold time of flop), uncertainty and CRPR.
25. what is start points and End points?
a) Start points are Input port, Q-pin of the flipflop.
End points are D-pin of the flip flop and Output port.