Library setup in Cadence Genus tool
Cadence Genus, Synopsys’s Fusion compiler and Design Compiler are the widely used synthesis tools in the industry. Setting up the […]
LIB,LEF and DEF
These files are the inputs for synthesis, floorplanning and are required for all the Physical Design stages. CONTENTS OF .LIB
Macro Placement Guidelines
There are some guidelines that need to be followed while placing macros to avoid congestion and other design problems from
Basic terminologies in Floorplan
Before jumping into floorplan implementation using tools like Innovus or ICC2, it’s essential to understand a few critical parameters. These
Why Floorplanning is important?
Floorplan in VLSI Physical Design Every subsequent stage like placement, routing and timing closure is dependent on how good your
Floorplanning in VLSI
What is Floorplanning? A floorplanning is the process of placing blocks/macros in the chip/core area,thereby determining the routing areas between them. Floorplan
Synthesis Flow in DC compiler
Cadence Genus and Synopsys DC Compiler are the two tools which are widely used in the industry for Synthesis Synthesis
Synthesis
What is Synthesis? The process of converting HDL design (Verilog or System Verilog) into a gate-level netlist is called synthesis.