26. There is a two version of tools (v1 ,v2) while loading same data in v1 tool it
won’t see any congestion while load in v2 i m seeing congestion what may be the
reason?
There are some variations in tool options from one version to another version. Some options will be enabled in one version by default, but in other it won’t be enabled. So due these variations we can see the variations in reports.
27. Before routing your timing was good but after routing you find more violations what may be the reason?
Before routing the net delays are estimated values, but after routing those are
accurate. So we can see some violations from previous stage.
While doing routing we will enable some options like SI aware (cross talk), so to avoid
cross talk issue some nets will be detoured due to this we get some timing violations.
During post route optimization some cells will be added in the design , due to this
we may get congestion.
28. If there are setup violations in placement stage, then how will you fix?
a) By applying path groups:
- group_path –name path1 –from starting points –to ending points
- setPathGroupOptions path1 -targetSlack 2
- optDesign –preCTS -incr
ii . Module constraint techniques : - createRegion modulename or groupname 100 100 4900 4900
- createFence modulename 100 100 1234 1234
29. Due to what reasons, we will see DRC’s?
a) If track availability is less then all metal will route through that track then we get
shorts, this may be due to more cell density at that area or pin density.
30. If you use normal buffers means what will happen?
a) For normal buffers the rise and fall times are not equal. When we use this normal buffers in
clock path , min pulse width violations may occurs.
31. What settings you will do for CTS?
- create_route_type –name clkroute –non_default_rule
2w2s – bottom_preferred_layer Metal5
to_preferred_layer metal6 - set_ccopt_property buffer_cells { CLKBUFX8 CLKBUFX12}
- set_ccopt_property inverter_cells { CLKINVX8 CLKINVX12}
- set_ccopt_property clock_gating_cells TLATNTSCA*
- create_ccopt_clock_tree_spec –file ccopt.spec
32. What is LEC?
a) LEC is logic equivalence check, LEC compares revised netlist and golden netlist, and it checks is both are logically equivalent or not that means functionality should be equal.
LEC inputs: Revised netlist , Golden netlist and .lib LEC FLOW:
- read golden netlist and read revised netlist and then read the libraries
- specifying design constraints
- mapping
resolving unmapped key points - Compare process
Debugging non-equivalent key points - Report run statistics
33. What is antenna violation and ways to fix it?
a) When a long metal is connected to the gate terminal charge accumulation takes place on the surface of the metal during the etching of plasma. This charge tries to discharge at gate and damages the gate oxide.
Ways to fix congestion:
Metal jogging:
This is preferred when the antenna effect occurs in lower metals. We split the metal near the gate and add a higher-level metal parallel to that. Only higher-level metal are preferred because during fabrication lower metals are fabricated first. If charge accumulation takes place, it can be removed by process known as rinsing.
Antenna diode:
This is preferred when the A.E occurs in higher metals. We connect it near the gate terminal in a reverse biased mode. As the charge flows breakdown occurs and no harm happens.
33. What are Decap cells?
a) Decap cells are temporary capacitors added in the design between power and ground rails to counter functional failures due to dynamic IR drop happens at the active edge of the clock at which a high percentage of sequential and digital elements switch.
At active edge of clock when the current requirement is high, these decaps discharge and provide boost to the power grid. One drawback of decap cells is that they are very leaky, so the more decap cells the more leakage.
34. What is Ocv, derates, uncertainty, jitter and what makes it to occur?
a) OCV (On chip variations) occurs due variations in PVT (process, voltage and temperature). Ocv is considered for single PVT.
Derates: PD side estimation of OCV in percentage.
Uncertainty: uncertainty includes skew , jitter and design
margin. Jitter : deviation of clock edge from its ideal location.
35. What is uncertainty before and CTS and After CTS?
a) Pre CTS:
uncertainty = skew + jitter + design
margin post CTS:
for setup: uncertainty = jitter + design
margin for hold: uncertainty = design
margin
36. Suppose you have 2 clock transition value 40ps and 50ps, and with both
your timing is met then what value you will choose?
we choose 40ps. if transition is less power dissipation also less. And speed increases.
37. What is ndm and how u will generate the NDM, what inputs you need to generate
NDM?
a) NDM (new data model) how to create NDM:
commit_workspace –output eg.ndm
create_workspace orca.dlib –use_technology_lib abc.ndm
read_db eg.db
read_db eg.lef
check_workspace
Inputs to NDM :
- .db and .lef
38. What is min density and why it is required?
a) If there are less no.of metals than specified in particular region then it results in min density violations. If there are min density violations it results in dishing effects, it causes opens.
39. How to balance insertion delay?
a) i. upsizing the cells
ii . removing buffers
40. what is path grouping? How do we do net weightage?
a) path grouping can be applied for in2reg paths, reg2reg paths and reg2out paths. The tool will optimize these paths based on the weightage value given to it.
Command:
- group_path -name anyname(path1) -from start point list –to end point
list – weight integer value(1,2 ,3 etc) - refine_opt -path_group path1
refine opt will do incremental optimization. In path grouping command we
have different sub options. By using this path grouping technique we can
optimize specific paths or nets.
41. what is scan clock and functional clock? How do we differentiate?
a) The frequency of test clock and functional clock is different. The functional clock
has more frequency than the test clock.
Because test clock is used in test mode to check the manufacturing defects of the flops and combinational elements(i.e. flops and combinational elements are working properly or not), to test this not much
frequency is required. the functional clock is used in functional mode to check the timing of the design.
By using set_case_analysis command we can differentiate which clock to propagate in our design.
42, Have you worked on multi clocks? How do we take care?
a) NO, I didn’t work on multi clock entering points. But I have idea if multiple clock
entry points are there in design.
We have two scenarios: multi clocks means clocks with different frequency . this clocks can have generated logic outside the block (i.e. in top level design) or inside our block.
i) If clock is generated inside the block ,then the tool will automatically balance the insertion delay and skew for those clocks by considering information mentioned in the spec file (like through pin).
But if the divided logic is in outside the block ( i.e if it presents in top level) then we need to apply clock grouping technique to balance the skew between those to clocks.
Multi clocks with different source then those clocks called as asynchronous
clocks. For asynchronous clocks no need to calculate timing.
43. we are getting clock net shorts, what may be possible reason?
a) may be at that area we have more no.of sequential elements. We are getting shorts means the available tracks are less than the required tracks this may be due to having more cell density at that particular area and main thing is most of the cells are flip flops. Congestion is not cleared at that area in placement stage.
44. what exactly happens in post CTS?
In post CTS, various optimizations will be done that includes: meeting DRV’s ,
setup and hold, Area and Power optimization, congestion reduction.
45. How channel spacing between macros is kept based on what factors?
A) channel spacing between macro’s = no.of pins x pitch / ((total no.of metal layers available)/2)
46. How do we reduce congestion?
a) congestion occurs mainly due to three reasons.
i. high cell density ii. high pin density iii. Bad floorplan techniques for reducing congestion are:
i. cell density : if congestion is due to cell density ,then apply partial blockages at
that area to reduce cell density in that region.
ii. Pin density : if congestion is due to pin density ,then apply cell padding techniques.
iii. bad floorplan (notches) : if we have congestion at macro edges ,
then apply hard blockages to reduce congestion.
47. What is the procedure to generate ndm?
a) icc2_lm_shell -f ndm_gen.tcl
48. what is difference between place.coarse.max_density and place.coarse.max_util?
A ) max_density: specify a maximum density that controls how densely the tool can place cells in uncongested areas during wire-length-driven placement.
place.coarse.max_density ( default is 0 and the tool spreads cells uniformly by
default)
max_util: Specify a congestion-driven maximum utilization that controls how densely the tool can place cells in less congested areas that surround highly congested areas, so that the cells in the congested areas can be spread out to reduce the congestion.
place.coarse.congestion_driven_max_util (Default is 0.93)
When specifying the maximum density or congestion-driven maximum utilization,
choose a value between 1 and the overall utilization of the block. For example, if the
utilization of a block is 40 percent; you can choose values between 1 and 0.4.
49. How do you check setup and hold for half cycle path?
Setup check: 5ns to
7.5ns Hold check : 5ns
to 2.5ns
50. How do you fix setup and hold on same path i.e. single start point and single end point? Reason?
There are two reasons for getting setup and hold on same path:
For setup we won’t remove CRPR value because setup check is done at different edges, the impact of delay variation at one clock edge is different from delay variation on cell at different clock edge so we consider those variations (CRPR) for setup check.
Whereas for hold check is done at same edge, so we remove the CRPR value for hold. Therefore, due to this CRPR, we may get setup and hold violation on same path.
If cell delay variations are more in data path from max lib to min lib, then we can get the setup and hold on same path.
Fixes:
we will swap the huge variation cells with less variation cells.
Reduce the common path by moving cells closure.