That includes 

    Reading the PG netlist 

    Reading the UPF

    Run low power checks called CLP

Make sure IN ICC your check_mv_design is clean

Chevk_mv_design:

•  To verify the power network definition for a multivoltage design, run the check_mv_design command. 
• This command checks for various types of violations such as inconsistent and conflicting library settings, missing isolation cells, and incorrect voltage shifting across power domains. •
• To check the power and ground connections, use the -power_connectivity option.
•  When you use this option, the tool checks the power and ground connections in addition to the power network definition, and updates the connections if it finds any issues. By default, it does not check the power and ground connections. 
• To specify the maximum number of messages for each violation type, use the -max_message_count option. By default, it reports a only 20 occurrences of a given violation type

Types of low  power checks

      Static Checks  

• Static checks detect architectural issues in the design.
• As a missing isolation or level shifter cell.
• Can be performed without running a simulation
• Save time and effort as you do not need to write a testbench. So you can run them on your low-power design as soon as the design is readyThere are two kinds of static checks: static RTL and static gate-level simulation (GLS) checks. The static RTL checks are run on RTL designs and static GLS checks on gate-level design

      Dynamic checks : Dynamic checks are performed on the design while running simulation. Dynamic checks detect behavioral issues in the design, such as incorrect power sequencing of power domains

Isolation cells

Isolation cells are additional cells inserted by the synthesis tools for isolating the buses/wires crossing from power-gated domain of a circuit to its always-on domain. 

They clamp the output node to a known voltage.

In the isolation list we specify the clamping value of the nets as logic 0 or logic 1 and accordingly the synthesis tool will insert isolation cells.

Level Shifter Cells

Level Shifters (LS) are special standard cells used in Multi Voltage designs to covert one voltage level to another. 

As Multi Voltage designs have more than one voltage domain, level shifters are used for all the signals crossing from one voltage domain to another voltage domain. 

Like isolation cells, level shifters are inserted by the synthesis tool

Low to High Level Shifters

Low to High LS are used for signals crossing from a lower voltage domain to higher voltage domain.

It basically amplifies the source signal so that it can be interpreted properly in the destination domain. 

Suppose a 0.7V signal is crossing from 0.7V voltage domain to 1.0V voltage domain.

Now in the lower voltage domain it corresponds to logic-1 but in higher voltage domain it is neither logic-1 nor logic-0, so the signal becomes unknown (or ‘X’) in the absence of Low to High LS.

High to Low Level Shifters

High to Low LS are used for signals crossing from higher voltage domain to lower voltage domain.
It basically attenuates the source signal. 

Although putting a LS for signals crossing from higher voltage domain to lower voltage domain is optional as signals will be interpreted properly in destination domain, but typically we put a LS to avoid stress on the transistors of lower voltage domain due to high voltage of the source signal.

Bi-directional Level Shifters

When dynamic voltage scaling or dynamic voltage frequency scaling is used the voltage relation between the source and destination might change over time of operation. In that case we need level shifter which is capable of shifting both low to high voltage signals and high to low voltage signals.

Retention cells

These cells are special flops with multiple power supply. They are typically used as a shadow register to retain its value even if the block in which its residing is shut-down.

 All the paths leading to this register need to be ‘always_on’ and hence special care must be taken to synthesize/place/route them. 

In a nut-shell, “When design blocks are switched off for sleep mode, data in all flip-flops contained within the block will be lost. If the designer desires to retain state, retention flip-flops must be used”.

The retention flop has the same structure as a standard master-slave flop. 

However, the retention flop has a balloon latch that is connected to true-Vdd. 

With the proper series of control signals before sleep, the data in the flop can be written into the balloon latch.

 Similarly, when the block comes out of sleep, the data can be written back into the flip-flop

What are all the low power checks?

Back-to-Back Checks

• Sometimes your design has back-to-back cells, which might be any of the following types:
• Isolation and level shifter cell
• Level shifter and isolation cell
• Isolation and isolation cell
• Level shifter and level shifter cell

Other checks

• The design cells have missing liberty attributes.
• The isolation, level shifter, or retention supply is powered-down during the active isolation, level shifting, or retention period.
• The power signal of a power domain gets corrupted.
• The input of a power domain toggles when the power domain is powered-down.
• The power state table or the supply port reaches an illegal or undefined state.

The post CLP Low Power Checks appeared first on Learn VLSI.

A Standard Cell is a group of transistor and its interconnect structures that provides a Boolean logic function (e.g., AND, OR, XOR, XNOR, Inverters) or a storage function (Flip-flop or Latch)

Types of Standard Cells

• Buffers (Inverting and Non-inverting )
• Combinational (AND, OR, NAND, NOR, AOI, OAI, OA, AO, MUX)
• Arithmetic (XOR, full-adder, half-adder), Sequential (latches, clockgates, D-type flip/flops with any optional combination of scan input, set and reset)
• Miscellaneous (ICG Cells, Well Taps, Tie Cells, End Caps, Decaps, Filler Cells, Spare Cells, Delay Cells, Antenna Diode, ESD diodes)

ICG Cells in CTS

Integrated Clock Gating Cells (ICG Cells)

• During idle modes, the clocks can be gated-off to save dynamic power dissipation on flip-flops
• Proper circuit is essential to achieve a gated clock state to prevent false glitches on clock path
• Use a combination of AND and a Latch to avoid any glitches on the clocks. A glitch can propagate a false edge on to the design

Insertion of ICG

• Manual insertion of ICG
  • The clock gating can be implemented through logic circuits and ICG’s
  • Most of Clock Gating Cells from vendor libraries have a RTL code
• Automated Insertion of ICG –
  • Some power aware tools insert the ICG’s through automated software algorithms

Types of Clock Gating Cells

• Latch Based Clock Gating Buffer for Neg-edge
  • The circuit employs a latch and OR gate with one input inverted
  • The output clock is always clock gated low when Enable is low
• Latch Based Clock Gating Buffer for Pos-edge
  • The circuit employs a latch with inverted clock input and a AND gate
  • The output clock is always clock gated HIGH when Enable is low

ICG module IO’s

• 3 input ports – clock, clock enable and test
• 1 output port – clock for gated clock

Well Taps

• Physical only cell which helps to tie MOS Substrate and N-Wells to VDD and GND levels, and thus avoid latch-up possibilities
• Switching circuits dump current into Well/ Substrate and if there is a high resistance between Well/ Substrate and the VDD/ GND grids the Substrate can be at different potential than VDD/ GND which causes latch-up
• Well Tap Cells reduce resistance between VDD/ GND to wells of the Substrate
• Tap Cells are usually placed on the Power Rails of the Standard Cells
• Standard Cells do not have internal tap to N-well (P substrate process) to reduce design complexity of Standard Cells
• These library cells do not have any signal connectivity
• Hence Tap to Wells is done by external cells called “Tap cells” which are sprinkled all over Core Area at regular distance as decided by the foundry
• More Taps reduces resistance, but will also increases core area, so we need a trade-off which will be provided by the foundry
• Place well taps at regular intervals throughout the design with the specified distances and snaps them to legal positions

End Cap cells in VLSI

• End-cap cells are preplaced physical-only cells required to meet certaindesign rules and placed at the ends of the site rows by satisfying well tie-off requirements for the core rows
• These library cells do not have any signal connectivity
• They connect only to the power and ground rails once power rails are created in the design
• They also ensure that gaps do not occur between the well and implant layers i.e. well proximity effect
• This prevents DRC violations by satisfying well tie-off requirements for the core rows
• Each end of the core row, left and right, can have only one end cap cell specified
• However, you can specify a list of different end caps for inserting horizontal end cap lines, which terminate the top and bottom boundaries of objects such as macros
• End caps have a fixed attribute and cannot be moved by optimization steps
• A core row can be fragmented (contains gaps), since rows do not intersect objects such as power domains. For this, the tool places end cap cells on both ends of the un-fragmented segment

Filler Cells

• Physical only cells which provide N-Well continuity and avoid N-Well spacing DRC
• Filler cells are inserting for density rules, to meet Core Utilization targets and to avoid sagging of layer
• Filler cells are inserting at the last stage of Placement and Routing
• Some of the small cells also don’t have the Bulk/Substrate connection because of their small size (thin cells)
• In those cases, the abutment of cells through inserting Filler Cells can connect those Substrates of small cells to VDD/ GND nets
• i.e. those thin cells can use the bulk connection of the other cells
• Filler cells are used to make up the Poly density (if that filler cell is having any poly structure inside), but certainly not for metal density
• Filler cells are also useful for ECO

Decap Cells

• Decaps are on-chip decoupling capacitors (Extrinsic Capacitances) that are attached to the power mesh to decrease noise effects (dynamic I.R. Drop)
• Supply voltage variations caused by Instantaneous Voltage Drop (IVD) lead to problems related to spurious transitions and delay variations
• Decap cells are typically poly gate transistors where source and drain are connected to the ground rail, and the gate is connected to the power rail
• Decap helps to smoothen out the Glitches and Ground bounce
• 3% to 8% of the core physical area is required for Decaps refered as decap density
• It is important to place only the necessary amount of decaps since they normally come with a quite serious down-side as they are leaky devices
• Another drawback, which many designers ignore, is the interaction of the decap cells with the package RLC network
• Since the die is essentially a capacitor with very small R and L, and the package is a hug RL network, the more decap cells placed the more chance of tuning the circuit into its resonance frequency. That would be trouble, since both VDD and GND will be oscillating
• NMOS Decaps are superior to PMOS decaps because of the high frequency operation and large REFF and CEFF for the same area

ESD Clamp

• ESD Clamp/ ESD Diode is the primary protection device that protects against ESD surges at the I/O pad by clamping the voltage and allowing the high ESD current to be discharged safely to the ground terminal
• The main function of ESD Clamp is to protect the Gate oxide
• Snap back device (Diode implementation between the grounds) provides Snapback voltage (ESD Voltage) to get grounded thus the ESD current won’t be getting in to Gate
• The design of ESD Clamp must ensure that Electrical Overstress (EOS) events do not cause failure
• The ESD Clamp is essential for HBM, MM, and CDM

Spare Cells

• Pre-placed inactive (with inputs tied off) gates in the empty areas of a design (or even in the crowded areas) before tape-out (Mostly NAND Gates)
• ECO Cells/ Spare Cells are collection of Gates coming in different sizes for doing small functional ECO and connect them with minimal mask changes called a metal-only ECO
• Provides new functions on a design which exhibits post-production problems
• No change is made to the diffusion layer, M1 and a contact layer only need to change
• Disadvantages:
  • They are connected to VSS and VDD and despite having their inputs tied off, they are still drawing Static Current
  • The designer may not have the right cell in the right place at the time of the ECO

Tie Cells

• Tie-high and Tie-Low cells are used to connect the Gate of the transistor to either Power or Ground
• In deep sub micron process, if the Gate is connected to Power/ Ground, the transistor might be turned ON/ OFF due to Power or Ground Bounce
• The suggestion from foundry is to use Tie Cells for the purpose
• The cells which require VDD, comes and connect to Tie High (so Tie High is a Power Supply Cell), while the cells which wants VSS connects itself to Tie-Low
• Without Tie Cells, unused inputs are tied to logic-high or logic-low, and these connections are made by routing the input pin right to the Power/ Ground grid
• With Tie Cells, unused inputs in the original netlist are tied to logic-high or logic-low, and somewhere during the physical design process, Tie Cells are inserted
• The unused inputs are then connected to a Tie-high or Tie-low Cell

Delay Cells

• Delay Cells
  • Are buffer cells with slower transition time
  • Can drive high currents
  • Are helpful in reducing Slew Rate (0-1 or 1-0 Transition Time)
  • Are of wider channel
  • Have delay starting from 20ps to few Nano seconds
  • Will have constant delay

Metrology Cells

• To enable the reliable re-productivity of micro-scale devices used in high volume and low cost
• To measure and monitor the process parameters during manufacturing
• The effect of process variations during fabrication time can be identified and measured

The post 11 Types of cells in VLSI Physical Design appeared first on Learn VLSI.

The idea here is to supply power througout the design.

Types of Power Planning

• core cell power management
• I/O cell power management

In core cell power management VDD and VSS power rings
are formed around the core and macro. In addition to this straps and trunks are created for macros
as per the power requirement.

In I/O cell power management, power rings are formed for I/O
cells and trunks are constructed between core power ring and power pads. Top to bottom
approach is used for the power analysis

Rings

Carries VDD and VSS around the chip

Stripes

Carries VDD and VSS from Rings across the chip

Rails

Connect VDD and VSS to the standard cell VDD and VSS.

2 methods of Power supply

Wirebond power supply

In wire bounded only the edges can be used.

Disadvantage:

• More IR drop
• Less Speed, needs more die area for IO limited design.

Flip-chip Power supply

Advantage:

• Small IR drop
• Very high speed design possible

Disadvantage:

• Heat sink problem
• Cost of flip-chip packing is more.
• Less reliable than wirebond.

Flip-Chip Basics

Flip the die upside down and the whole surface can be connected to package in principle.

• Opportunity to add voltage sources to the core regions- but must have adequate ESD protection
• Opportunity to reduce die size (less core supply cells in the IO ring; less IO PG supply cells in the IO ring; IO cells could be abutted)
• The bumping process can be expensive
• The substrate routing problem is more difficult (binding posts have larger separation than bump pads) A more expensive substrate may be required
• The Package can in principle be same size as the die
• Potentially faster operation as wire bond inductance is avoided. 

Two types of flipchips being designed currently.

   Peripheral IO flipchip.

   Area IO flipchip.

Peripheral IO flipchip

Most IO cells remain in a conventional ring

IO cells can be abutted in Single Rows of IO cells

Dual Rows of IO cells can also be used

IO cells connect to bump pads via the redistribution layer (RDL). From bump pads we connect to bumps and then the package.

Limited benefits in terms of die size reduction

It may be possible to add core PG voltages directly to the core region. This would reduce the number of IO cells in the ring, reduce die size, and improve the voltage drop.

Area IO flipchip

IO cells are placed in the core region as well as the ring.

A big opportunity to reduce the die size

Opportunity to reduce voltage drop

Many unknowns: noise in core; large blockages in core

Probably requires a totally new class of IO cell library to be developed

IO cells connect to the package via RDL routing, but less RDL routing is required.      

The post Power Planning appeared first on Learn VLSI.

CONTENTS OF .LIB

• The information inside the Lib file can be divided into two main parts.
• In the first part, it contains some information which is common for all the standard cells.
• The common part of Lib file contains : 1) Library name and technology name 2) Units (of time, power, voltage, current, resistance and capacitance) 3) Value of operating condition ( process, voltage and temperature) – Max, Min and Typical
• Cell delay is a function of input transition and output load and is calculated based on lookup tables.
• Cell delays are calculated by Nonlinear Delay Model(NLDM) and composite current source (CCS) models.
• Based on operating conditions there are three different lib files for Max, Min and Typical corner

• In the second part of Lib file, it contains cell-specific information for each cell. The part of Lib file which contains cell-specific information is shown below.

Cell-specific information in Lib file is mainly:

1) Cell name

2) PG Pin name

3) Area of cell

4) Leakage power in respect of input pins logic state

5) Pins details

CONTENTS OF LEF

• A LEF file is used by the router tool in PnR design to get the location of standard cells pins to route them properly.
• So it is basically the abstract form of layout of a standard cell.
• A LEF file describing the Library has mainly two parts.

1) Technology LEF

2) Cell LEF

.tech.lef (Cadence format)

.tf – technology file ( Synopsys format)

1) TECHNOLOGY FILE

• Technology LEF part contains the information regarding all the metal interconnects, via information and related design rules whereas cell LEF part contains information related to the geometry of each cell. A sample snapshot is given below to show the information under technology LEF part.

• Technology LEF part contains the following information

1) LEF Version ( like 5.7 or 5.8 )

2) Units (for database, time,  resistance, capacitance)

3) Manufacturing grids 

4) Design rules and other details of BEOL (Back End Of Layers)

• Layer name (like poly, contact, via1, metal1 etc)
  • Layer type ( like routing, masterslice, cut etc)
  • Preferred direction (like horizontal or vertical)
  • Pitch
  • Minimum width
  • Spacing 
  • Sheet resistance

2) CELL LEF

• Cell LEF part contains the information related to each cell present in the standard cell library in separate sections.

• Cell LEF basically contains the following information

1) Cell name (like AND2X2, CLKBUF1 etc)

2) Class ( like CORE or PAD)

3) Origin 0 0

4) Size (width x height)

5) Symmetry ( like XY, X, Y etc)

6) Pin Information

• Pin name (like A, B, Y etc)
  • Direction (like input, output, inout etc )
  • Use (like Signal, clock, power etc)
  • Shape  (Abutment in case of power pin)
  • Layer (like Metal1, Metal2 etc )

The rectangular coordinate of pin (llx lly urx ury).

Technology specific inputs

CONTENTS OF DEF

• DEF file is used to represent the Physical layout of an Integrated Circuit (IC) in ASCII format.

• A DEF file contains the design-specific information of the circuit and it is a representation of the design at any point during the physical design. DEF conveys logical design data and physical design data. Logical design data includes internal connectivity (represented by netlist), group information and physical constraints. Physical data includes placement location and orientation of components and routing geometry.

• A standard DEF file contains mainly following sections and order of statement is also important.

• [ VERSION statement ]
• [ DIVIDERCHAR statement ]
• [ BUSBITCHARS statement ]
• [ DESIGN statement ]
• [ TECHNOLOGY statement ]
• [ UNITS statements ]
• [ DIAAREA statement ]

• [ ROW statement ]
• [ TRACKS statement ]
• [ CELLGRID statement ]
• [ VIAS statements ]

• [ NONDEFAULTRULES statement ]
• [ COMPONENTS statement ]
• [ PINS section ]
• [ BLOCKAGE section ]

• [ FILLS section ]
• [ SPECIALNETS section ]
• [ NETS section ]
• [ SCANCHAINS section ]
• [ GROUPS section ]
• [ BEGINEXT section ]
• END DESIGN statement

Header statement:

ROW statement:

Track statement:

GCell Grid statement:

Via statement:

All vias consist of shapes on three Layers

1.A cut layer

2.Two routing (or masterslice) layers that connect through that cut layer

Component section

Pin section:

•It defines external pins

•Each pin definition assigns a pin name for the external pin and associates the pin name with a corresponding internal net name

•The pin name and the net name can be the same.

Blockage section:

•Defines placement and routing blockages in the design

•PUSHDOWN : Specifies that the blockage was pushed down into the block from the top level of the design

Net section:

The post LIB,LEF and DEF appeared first on Learn VLSI.

Macros and all other logics will be sitting outside the die area, once the core and die gets created.

What are macros?

Macros are larger functional blocks like the IC’s memories (SRAM, ROM), analog devices (DAC, ADC), clock macros (PLLs), or interface macros. These macros are typically provided by third-party IP (Intellectual Property) vendors or developed in-house by the design team. Some of the qualities of a macro are:

1. They consume a larger area.
2. They are power-hungry devices i.e. they consume huge power.
3. They are placed at the boundary of the core area.

After executing shape_blocks command, tool will do a rough placement of macros.

Macro Placement guidelines:

What guidelines should I follow when placing hard macros in the floorplan?

This solution provides designers performing physical design (Place & Route) with tips and guidelines to create an initial floorplan. These guidelines will help you maximize the space available for standard cell placement, avoid routing congestion problems, and achieve the power supply routing requirements.

This solution focuses on two main areas to help you achieve high-density designs:

• Macro Placement
• Row Generation

These tips range from simple guidelines to more advanced ones that may or may not apply to your design. For your design, you also have to take into account specific conditions and constraints such as:

• Timing
• Clock
• Power
• IP specific restriction
• DFT test

1. Place macros around chip periphery

If you do not have a rationale to place the macro inside the core area, place macros around the chip periphery. Placing a macro inside the core can invite serious consequences during routing due to a lot of detour routing.

This is because macros are equal to a large obstacle for routing. Also, placing the hard macros around the core-periphery makes it easier to supply power to these macros, and reduces the chance of IR drop problems for macros consuming high amounts of power.

2. Consider connections to fixed cells when placing macros

When you decide the macro position, you have to pay attention to connections to fixed elements such as I/O and pre-placed macros. Place macros near the corresponding associate fixed elements. Check connections by displaying flight lines in the GUI.

 3. Orient macros to minimize the distance between pins

When you decide the orientation of macros, you also have to take into account the positions of the pins and the respective connections.

4. Reserve enough room around macros

For regular net routing and power grid, you have to reserve enough routing space around macros. In this case, estimating routing resources with precision is very important. 

Use the congestion map from trialRoute to identify hotspots between macros and adjust the placement as needed.

5. Reduce open fields as much as possible

Except for reserved routing resources, remove dead space to increase the area for random logic.

Choosing a different aspect ratio (if that option is available) can eliminate open fields.

6. Reserve space for power grid

The number of required power routes can change based on the power consumption.

You have to estimate the power consumption and reserve enough room for the power grid. If you underestimate the space required for power routing, you can encounter routing problems.

Note: At least one pair of metal layer tracks must be between two macros. This pair of tracks will be used as Vss and Vdd in the power planning stage. If the standard cell is present between the macros and if the metal layers between the macros are not, then this will lead to an IR drop.

The post Macro Placement Guidelines appeared first on Learn VLSI.

1. Core Area

The core area is the central region of the die (the complete chip) where all types of cells are placed. This includes:

• Standard cells

• Macros

• Blockages

• Physical-only cells

Important: No cells can be placed outside the core area. The placement engine works strictly within this boundary.

Formula to calculate core size:

Core size = (Standard cell area + Macro area + Blockages area) / Standard cell utilization

This ensures you allocate enough space for cells while considering your target utilization.

2. Aspect Ratio

The aspect ratio determines the shape of the core area. It’s the ratio of height to width.

Formula:

Aspect ratio = Height of core area / Width of core area

• If the aspect ratio is 1.0, the core is a square.

• If it’s 0.5, the core is wider (width = 2 × height).

• If it’s 2.0, the core is taller (height = 2 × width).

This impacts how well the routing engine can handle congestion. Some routing patterns work better in square or slightly rectangular regions depending on design constraints.

Alternative formula (tool-specific):

Aspect ratio = Horizontal routing tracks / Vertical routing tracks

The number of routing tracks in horizontal/vertical directions influences the actual shape and routing capacity.

3. Routing Tracks

A routing track is a virtual line on a metal layer used to guide routes. These don’t physically exist but act as reference paths for router algorithms.

• Routing tracks run horizontally or vertically.

• The distance between two tracks is called pitch.

• Routers snap nets to these tracks for efficient alignment and DRC compliance.

These tracks are tightly packed and follow the design rules of the technology.

4. Utilization

Utilization defines how much of the core area is occupied by cells.

Formula:

Utilization = (Standard cell area + Macro area) / Core area × 100%

• Typically, standard cells use 70% of the area, and routing uses the remaining 30%.

• However, if your design has large macros, you may need to reduce standard cell utilization to ensure there’s still room for routing.

Tip: Over-utilizing space will lead to routing congestion and timing violations. Under-utilizing wastes silicon.

5. Manufacturing Grid

The manufacturing grid defines the minimum resolution the foundry can fabricate on silicon. It represents the smallest step size or point on a grid where a feature can be drawn.

• Found in your tech LEF file.

• Example: A manufacturing grid of 0.005 µm means you can’t define geometries smaller than this step.

This grid ensures layout precision and foundry compatibility.

6. Standard Cell Site

A standard cell site is the basic unit size in a floorplan where cells can be placed.

• It has minimum width and height, and all standard cells are placed in multiples of this size.

• Even filler cells (used to fill gaps) occupy one or more sites.

Knowing site size helps you visualize and optimize row placement and macro fitting.

7. Standard Cell Rows

The core area is divided into rows, and these rows are where standard cells are placed.

• All rows have fixed height, and standard cells align within these rows.

• The width of the standard cells may vary, but the height is always a multiple of the site height.

This alignment ensures:

• Power rails (VDD/VSS) match

• Clean placement

• No DRC violations

8. Inverted Rows

To share power rails efficiently, alternate rows are inverted.

Example:

• Row 1: VDD on top, VSS on bottom

• Row 2: VSS on top, VDD on bottom

Why?

• Cells in adjacent rows can share the same VSS/VDD rails.

• This saves routing resources and core area.

If you don’t follow this inverted row structure, you’d need to leave extra space between rows, wasting valuable area.

A good floorplan is the foundation of a successful physical design flow. Understanding and correctly applying:

• Core size

• Aspect ratio

• Routing tracks

• Utilization

• Manufacturing grid

• Cell sites and rows

…ensures your layout is not only functional but also optimized for timing, area, and power.

The post Basic terminologies in Floorplan appeared first on Learn VLSI.

Every subsequent stage like placement, routing and timing closure is dependent on how good your foorplan is. In a real time design, you go through many iterations before you arrive at an optimum floorplan.

Floorplanning takes in some of the geometrical constraints in a design. Examples of this are:

• Bonding pads for off-chip connections (often using wire bonding) are normally located at the circumference of the chip.
• Line drivers often have to be located as close to bonding pads as possible.
• Chip area is therefore in some cases given a minimum area in order to fit in the required number of pads.
• Areas are clustered in order to limit data paths thus frequently featuring defined structures such as cache RAM, multiplier, barrel shifter, line driver and arithmetic logic unit.
• Purchased intellectual property blocks (IP-blocks), such as a processor core, come in predefined area blocks.
• Some IP-blocks come with legal limitations such as permitting no routing of signals directly above the block.

Need of Floorplanning

The first step in the Physical Design flow is Floor Planning. Floorplanning is the process of identifying structures that should be placed close together, and allocating space for them in such a manner as to meet the sometimes conflicting goals of available space (cost of the chip), required performance, and the desire to have everything close to everything else.

    Based on the area of the design and the hierarchy, a suitable floorplan is decided upon. Floor Planning takes into account the macro’s used in the design, memory, other IP cores and their placement needs, the routing possibilities and also the area of the entire design.

Floor planning also decides the IO structure, aspect ratio of the design.

A bad floor-plan will lead to waste-age of die area and routing congestion.

    In many design methodologies, Area and Speed are considered to be things that should be traded off against each other.

The reason this is so is probably because there are limited routing resources, and the more routing resources that are used, the slower the design will operate.

Optimizing for minimum area allows the design to use fewer resources, but also allows the sections of the design to be closer together.

This leads to shorter interconnect distances, less routing resources to be used, faster end-to-end signal paths, and even faster and more consistent place and route times.

Done correctly , there are no negatives to Floor-planning.

As a general rule, data-path sections benefit most from Floorplanning, and random logic, state machines, and other non-structured logic can safely be left to the placer section of the place and route software.

    Data paths are typically the areas of your design where multiple bits are processed in parallel with each bit being modified the same way with maybe some influence from adjacent bits. Example structures that make up data paths are Adders, Subtractors, Counters, Registers, and Muxes.

The post Why Floorplanning is important? appeared first on Learn VLSI.

A floorplanning is the process of placing blocks/macros in the chip/core area,thereby determining the routing areas between them.

Floorplan determines the size of die and creates wire tracks for placement of standard cells. It creates power ground(PG) connections.

It also determines the I/O pin/pad placement information.

Before starting with the floorplan we will perform import design, sanity checks and partitioning.

Sanity checks in Floorplanning

Sanity Checks mainly checks the quality of netlist in terms of timing.
— It also consists of checking the issues related to Library files, Timing Constraints, IOs and Optimization Directives

1. Library checks
    • Missing cell information
    • Missing pin information
    • Duplicate cells

2. Design checks
    • Inputs with floating pins
    • Nets with tri-state drivers
    • Nets with multiple drivers
    • Combinational loops
    • Empty modules
    • Assign statements

3. Constraint checks
    • All flops are clocked or not
    • There should not be unconstraint paths
    • Input and output delays

Goals of Floorplanning:

A good floorplanning should meet the following constrains.

•Minimize the total chip area

•Make routing phase easy (routable)

•Improve the performance by reducing signal delays.

Inputs for floorplan:

• Netlist (.v/ .vhd/ .edif)
• Physical Libraries (.lef)
• Timing Libraries (.lib)
• Technology Files
• Constraints (.sdc)

Core area is approximately calculated by the tool from the Netlist

Note: LEF and Lib files need to be loaded before importing the design

Output of floorplan:

• Die/Block area
• I/O pad/placed
• Macro placed
• Power grid design
• Power pre-routing

Steps in Floorplan

• Initialize with Chip & Core Aspect Ratio (AR)
• Initialize with Core Utilization
• Initialize Row Configuration & Cell Orientation
• Provide the Core to Pad/ IO spacing (Core to IO clearance)
• Pins/ Pads Placement
• Macro Placement by Fly-line Analysis
• Macro Placement requirements are also need to consider
• Blockage Management (Placement/ Routing)

IO Placement

• Chip Level its IO Pads and Block Level its IO Pins
• Pin is a logical entity and is a property of a Port
• Port is a physical entity and a Port have only 1 Pin associated with it
• Netlist will have Pins and Layout will have Ports
• Unplaced Port is not represented in the Layout

Floorplan Qualification:

• No I/O ports short
• All I/O ports should be placed in routing grid
• All macros in placement grid
• No macros overlapping
• Check PG connections (For macros & pre-placed cells only)
• All the macros should be placed at the boundary
• There should not be any notches. If unavoidable, proper blockages has to be added
• Remove all unnecessary placement blockages & routing blockages (which might be put during floor-plan & pre-placing)

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