Interview QA

1. Why are we not checking the hold before CTS? Before CTS, clock is ideal that means exact skew is

CMOS Fundamentals Q1. Why low power has become an important issue in the present day VLSI circuit realization? Answer:In deep

Physical Design Interview Questions with Answers 1. What is the physical design in VLSI industry? In VLSI, physical design (is

 1. Draw NAND/ NOR gate using CMOS? 2. What is tie-high and tie-low cells? TIEH & TIEL cells are used

1.what are half cycle paths? In half cycle path which one is critical? Setup or hold? A path which requires

Questions 101 to 120 101. Tell me flow RTL onwards? 102. What is meant by empty modules? For module, it

Questions 81 to 100 ASIC PD Interview Questions 81. what is cross talk? Cross talk is the transfer of a

Questions 61 to 80 ASIC PD Questions with Answers 61. How to fix setup and hold violations? a) setup fixes: